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參數(shù)資料
| 型號： | MPC5534MVM80 |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 14/60頁 |
| 文件大小： | 0K |
| 描述： | MCU 1MB FLASH 80MHZ 208MAPBGA |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 系列： | MPC55xx Qorivva |
| 核心處理器： | e200z6 |
| 芯體尺寸： | 32-位 |
| 速度： | 80MHz |
| 連通性： | CAN，EBI/EMI，以太網(wǎng)，SCI，SPI |
| 外圍設(shè)備： | DMA，POR，PWM，WDT |
| 輸入/輸出數(shù)： | 192 |
| 程序存儲器容量： | 1MB（1M x 8） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 64K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 1.35 V ~ 1.65 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 34x12b |
| 振蕩器型： | 外部 |
| 工作溫度： | -40°C ~ 125°C |
| 封裝/外殼： | 208-BGA |
| 包裝： | 托盤 |
| 其它名稱： | Q4437099 T0850514 |
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Electrical Characteristics
MPC5534 Microcontroller Data Sheet, Rev. 6
Freescale Semiconductor
21
19
CLKOUT period jitter, measured at fSYS max:
13, 14
Peak-to-peak jitter (clock edge to clock edge)
Long term jitter (averaged over a 2 ms interval)
CJITTER
—
5.0
0.01
%
fCLKOUT
20
Frequency modulation range limit 15
(do not exceed fsys maximum)
CMOD
0.8
2.4
%fSYS
21
ICO frequency
fico = [ fref_crystal (MFD + 4) ] (PREDIV + 1)
16
fico = [ fref_ext (MFD + 4) ] (PREDIV + 1)
fico
48
8017
MHz
22
Predivider output frequency (to PLL)
fPREDIV
420 18
MHz
1 Nominal crystal and external reference values are worst-case not more than 1%. The device operates correctly if the frequency
remains within ± 5% of the specification limit. This tolerance range allows for a slight frequency drift of the crystals over time.
The designer must thoroughly understand the drift margin of the source clock.
2 All internal registers retain data at 0 Hz.
3 Up to the maximum frequency rating of the device (refer to Table 1).
4 Loss of reference frequency is defined as the reference frequency detected internally, which transitions the PLL into self-clocked
mode.
5 The PLL operates at self-clocked mode (SCM) frequency when the reference frequency falls below f
LOR. SCM frequency is
measured on the CLKOUT ball with the divider set to divide-by-two of the system clock.
NOTE: In SCM, the MFD and PREDIV have no effect and the RFD is bypassed.
6 Use the EXTAL input high voltage parameter when using the FlexCAN oscillator in crystal mode (no quartz crystals or
resonators). (Vextal – Vxtal) must be 400 mV for the oscillator’s comparator to produce the output clock.
7 Use the EXTAL input low voltage parameter when using the FlexCAN oscillator in crystal mode (no quartz crystals or
resonators). (Vxtal –Vextal) must be 400 mV for the oscillator’s comparator to produce the output clock.
8 I
xtal is the oscillator bias current out of the XTAL pin with both EXTAL and XTAL pins grounded.
9 C
PCB_EXTAL and CPCB_XTAL are the measured PCB stray capacitances on EXTAL and XTAL, respectively.
10 This specification applies to the period required for the PLL to relock after changing the MFD frequency control bits in the
synthesizer control register (SYNCR). From power up with crystal oscillator reference, the lock time also includes the crystal
startup time.
11 PLL is operating in 1:1 PLL mode.
12 V
DDE = 3.0–3.6 V.
13 Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f
sys.
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise
injected into the PLL circuitry via VDDSYN and VSSSYN and variation in crystal oscillator frequency increase the jitter percentage
for a given interval. CLKOUT divider is set to divide-by-two.
14 Values are with frequency modulation disabled. If frequency modulation is enabled, jitter is the sum of (jitter + Cmod).
15 Modulation depth selected must not result in f
sys value greater than the fsys maximum specified value.
16 f
sys = fico (2
RFD).
17 The ICO frequency can be higher than the maximum allowable system frequency. For this case, set the FMPLL synthesizer
control register reduced frequency divider (FMPLL_SYNCR[RFD]) to divide-by-two (RFD = 0b001). Therefore, for a 40 MHz
maximum device (system frequency), program the FMPLL to generate 80 MHz at the ICO output and then divide-by-two the
RFD to provide the 40 MHz clock.
18 Maximum value for dual controller (1:1) mode is (f
MAX 2) with the predivider set to 1 (FMPLL_SYNCR[PREDIV] = 0b001).
Table 12. FMPLL Electrical Specifications (continued)
(VDDSYN = 3.0–3.6 V; VSS = VSSSYN = 0.0 V; TA = TL to TH)
Spec
Characteristic
Symbol
Minimum
Maximum
Unit
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