參數(shù)資料
型號: MPC5200CVR400B
廠商: Freescale Semiconductor
文件頁數(shù): 6/80頁
文件大?。?/td> 0K
描述: IC MPU 32BIT 400MHZ 272-PBGA
特色產(chǎn)品: MPC5200 Microcontroller
標(biāo)準(zhǔn)包裝: 40
系列: MPC52xx
核心處理器: e300
芯體尺寸: 32-位
速度: 400MHz
連通性: CAN,EBI/EMI,以太網(wǎng),I²C,IrDA,J1850,SPI,UART/USART,USB
外圍設(shè)備: AC'97,DMA,I²S,POR,PWM,WDT
輸入/輸出數(shù): 56
程序存儲器類型: 外部程序存儲器
RAM 容量: 16K x 8
電壓 - 電源 (Vcc/Vdd): 1.42 V ~ 1.58 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 272-BBGA
包裝: 托盤
MPC5200 Data Sheet, Rev. 4
Electrical and Thermal Characteristics
Freescale Semiconductor
14
3.2.4
G2_LE Core PLL Electrical Characteristics
The internal clocking of the G2_LE core is generated from and synchronized to the system clock by means
of a voltage-controlled core PLL.
3.3
AC Electrical Characteristics
Hyperlinks to the indicated timing specification sections are provided below.
AC Test Timing Conditions:
Unless otherwise noted, all test conditions are as follows:
Table 11. G2_LE PLL Specifications
Characteristic
Symbol
Notes
Min
Typical
Max
Unit
SpecID
G2_LE frequency
fcore
1
NOTES:
1
The XLB_CLK frequency and G2_LE PLL Configuration bits must be chosen such that the resulting system
frequencies, CPU (core) frequency, and G2_LE PLL (VCO) frequency do not exceed their respective maximum or
minimum operating frequencies.
50
550
MHz
O4.1
G2_LE cycle time
tcore
2.85
40.0
ns
O4.2
G2_LE VCO frequency
fVCOcore
400
1200
MHz
O4.3
G2_LE input clock frequency
fXLB_CLK
25
367
MHz
O4.4
G2_LE input clock cycle time
tXLB_CLK
2.73
50.0
ns
O4.5
G2_LE input clock jitter
tjitter
2
This represents total input jitter - short term and long term combined - and is guaranteed by design. Two different
types of jitter can exist on the input to core_sysclk, systemic and true random jitter. True random jitter is rejected, but
the PLL. Systemic jitter will be passed into and through the PLL to the internal clock circuitry, directly reducing the
operating frequency.
150
ps
O4.6
G2_LE PLL relock time
tlock
3
Relock time is guaranteed by design and characterization. PLL-relock time is the maximum amount of time required
for the PLL lock after a stable Vdd and core_sysclk are reached during the power-on reset sequence. This
specification also applies when the PLL has been disabled and subsequently re-enabled during sleep modes.
100
sO4.7
相關(guān)PDF資料
PDF描述
VI-21B-IY CONVERTER MOD DC/DC 95V 50W
MCIMX31CJMN4D MPU MX31 ARM11 473MAPBGA
V48C5M100BL CONVERTER MOD DC/DC 5V 100W
PD0070WH16138BH1 CAP CER 160PF 13KV 20% CHASSIS
PD0070WH12138BH1 CAP CER 120PF 13KV 20% CHASSIS
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MPC5200CVR400B 制造商:Freescale Semiconductor 功能描述:IC, 32BIT PROCESSOR
MPC5200CVR400BR2 制造商:Freescale Semiconductor 功能描述:MPU MPC52XX RISC 32BIT 400MHZ 2.5V/3.3V 272BGA - Tape and Reel
MPC5200CVR466B 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:SDRAM/DDR Memory Controller
MPC5200ID 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:MPC5200 Hardware Specifications
MPC5200VR400 功能描述:微處理器 - MPU NO-PB COMM 5200 400MHZ RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324