參數(shù)資料
型號: MPC5200CVR400B
廠商: Freescale Semiconductor
文件頁數(shù): 10/80頁
文件大?。?/td> 0K
描述: IC MPU 32BIT 400MHZ 272-PBGA
特色產品: MPC5200 Microcontroller
標準包裝: 40
系列: MPC52xx
核心處理器: e300
芯體尺寸: 32-位
速度: 400MHz
連通性: CAN,EBI/EMI,以太網,I²C,IrDA,J1850,SPI,UART/USART,USB
外圍設備: AC'97,DMA,I²S,POR,PWM,WDT
輸入/輸出數(shù): 56
程序存儲器類型: 外部程序存儲器
RAM 容量: 16K x 8
電壓 - 電源 (Vcc/Vdd): 1.42 V ~ 1.58 V
振蕩器型: 內部
工作溫度: -40°C ~ 85°C
封裝/外殼: 272-BBGA
包裝: 托盤
MPC5200 Data Sheet, Rev. 4
Electrical and Thermal Characteristics
Freescale Semiconductor
18
NOTE
Beware of changing the values on the pins of the reset configuration word
after the deassertion of PORRESET. This may cause problems because it
may change the internal clock ratios and so extend the PLL locking process.
3.3.4
External Interrupts
The MPC5200 provides three different kinds of external interrupts:
Four IRQ interrupts
Eight GPIO interrupts with simple interrupt capability (not available in power-down mode)
Eight WakeUp interrupts (special GPIO pins)
The propagation of these three kinds of interrupts to the core is shown in the following graphic:
Figure 4. External interrupt scheme
Due to synchronization, prioritization, and mapping of external interrupt sources, the propagation of
external interrupts to the core processor is delayed by several IP_CLK clock cycles. The following table
specifies the interrupt latencies in IP_CLK cycles. The IP_CLK frequency is programmable in the Clock
Distribution Module (see Note Table 16).
Table 16. External interrupt latencies
Interrupt Type
Pin Name
Clock Cycles
Reference Clock
Core Interrupt
SpecID
Interrupt Requests
IRQ0
10
IP_CLK
critical (cint)
A4.1
IRQ0
10
IP_CLK
normal (int)
A4.2
IRQ1
10
IP_CLK
normal (int)
A4.3
IRQ2
10
IP_CLK
normal (int)
A4.5
IRQ3
10
IP_CLK
normal (int)
A4.6
8 GPIOs
GPIO WakeUp
GPIO Std
IRQ0
IRQ1
IRQ2
IRQ3
PIs
cint
int
Grouper
Encoder
Main Interrupt
Controller
core_cint
core_int
G2_LE Core
Notes:
1. PIs = Programmable Inputs
2. Grouper and Encoder functions imply programmability in software
8
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