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參數(shù)資料
| 型號(hào)： | MPC505 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Highly Integrated, Low-Power, 32-Bit Microcontroller |
| 中文描述： | 32-BIT, RISC MICROCONTROLLER, PQFP16 |
| 文件頁(yè)數(shù)： | 8/12頁(yè) |
| 文件大?。?/td> | 68K |
| 代理商： | MPC505 |
Application Note
AN1281
8
MOTOROLA
How Long
Interrupts
are Disabled
As long as interrupts are disabled (EE bit reset in the MSR), additional
interrupts are not recognized. To minimize latency of the next interrupt,
the interrupt handler should be as short as possible (unless the handler
routines check for higher priority interrupts during its processing).
Non-Maskable
Exceptions During
Interrupt Handler
Routines
When an exception occurs, hardware automatically saves the state of
the machine in registers SRR0 and SRR1. When another exception
occurs, the contents of SRR0 and SRR1 are overwritten. If the machine
state of an exception is lost, the program cannot recover.
Interrupts can be masked, but most exceptions are non-maskable. To
minimize the risk of being unable to recover from nested exceptions,
take these precautions when writing interrupt or other exception
handlers:
1.
Save registers that can be altered by non-maskable exceptions
early in the handler, preferably in the prologue. These registers
include SRR0 and SRR1, and in certain exceptions the DAR and
DSISR registers.
2.
Once these registers are saved, set the recoverable interrupt (RI)
bit in the machine status register.
3.
Ensure that exception-generating instructions (like “system call”)
are not executed during the prologue or epilogue (between
restoring of these registers and execution of the “rfi” instruction).
Example Interrupt Handler
The steps for an interrupt handler vary by application, but the issues are
similar.
Table 4
shows a general case. Some general-purpose registers
must be used, so the previous contents of these registers needs to be
stored (typically on the stack) and then restored before the end of the
handler.
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