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參數(shù)資料
| 型號： | MPC505 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Highly Integrated, Low-Power, 32-Bit Microcontroller |
| 中文描述： | 32-BIT, RISC MICROCONTROLLER, PQFP16 |
| 文件頁數(shù)： | 6/12頁 |
| 文件大小： | 68K |
| 代理商： | MPC505 |
Application Note
AN1281
6
MOTOROLA
Initialize PIT
An initial 16-bit PIT value is loaded into the periodic interrupt timer (PIT)
register. When the PIT is enabled, the register is automatically
decremented, and an interrupt service request is made each time the
count passes through zero. The initial value is automatically reloaded
into the register after each PIT time-out.
The periodic interrupt control and select register (PICSR) controls the
PIT. Bits and fields in PICSR perform the following functions:
Select PIT clock frequency
Define the 16-bit count value for the PIT
Enable the PIT counter
Enable the PIT interrupt
Indicate PIT status (report whether a PIT interrupt request has
been asserted)
Enable Individual
Interrupts
Load the IRQENABLE register with a value to enable the desired
interrupt levels. A level is enabled by setting the corresponding bit to one
or disabled by clearing the corresponding bit to zero. For example,
setting bit 2 of IRQENABLE enables interrupt level 2.
Enable External
Interrupts
Following reset, all interrupts and other exceptions are disabled. To
enable interrupts, the external enable (EE) bit in the machine state
register (MSR) must be set. The recoverable interrupt (RI) bit must also
be set. This topic is discussed in subsequent sections. Both the EE and
RI bits can quickly be set by using one of the special purpose registers
(SPR) called the external interrupt enable (EIE). The only purpose of the
EIE is to efficiently set the EE and RI bits, which is accomplished by
loading any value to EIE.
In the PowerPC architecture, an SPR must be loaded from a general-
purpose register using the move to SPR instruction. Any GPR can be
used as a source. The following code enables interrupts and sets RI:
mstpr
EIE, gpr0
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