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參數(shù)資料
| 型號(hào)： | MPC505 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Highly Integrated, Low-Power, 32-Bit Microcontroller |
| 中文描述： | 32-BIT, RISC MICROCONTROLLER, PQFP16 |
| 文件頁(yè)數(shù)： | 10/12頁(yè) |
| 文件大?。?/td> | 68K |
| 代理商： | MPC505 |
Application Note
AN1281
10
MOTOROLA
Set the
Recoverable
Interrupt Bit
Once the previous state is saved or copied into memory, it is possible to
recover if a non-maskable exception occurs. The recoverable interrupt
bit in the MSR must be set to communicate to any non-maskable
exception routine that recovery is possible.
Once again, a special purpose register has been implemented to quickly
assist this operation. Loading any value to the external interrupt disable
(EID) SPR sets the RI bit in the MSR while keeping interrupts disabled
(EE bit 0). Again, any GPR could be used to write to that SPR, since the
content of the GPR is unaltered. For example:
mtspr
EID, gpr0
Identify Interrupt
Source
Read the IRQAND register (IRQAND = IRQENABLE IRQPEND) to
identify which enabled level caused the interrupt. Under the priority
scheme set up during initialization, the most significant bit is the higher
priority interrupt to be serviced. The PowerPC instruction “count leading
zeros in the word” (cntlzw) can be used to identify the set bit in a register.
This instruction counts the number of consecutive zero bits starting at bit
0, the most significant bit. The result, from 0 through 32, is put in the first
register operand.
The following code identifies the source interrupt. Since a GPR is
required, the same GPR is used as before for temporary storage.
lis
gpr4, SIUBASE_UPPER (gpr0)
ori
gpr4, IRQAND_OFFSET (gpr3)
cntlzw
gpr4, gpr4
# Load SIU base addr
# Index to IRQAND
# Find level number
Branch to
Appropriate
Routine
There are a number of ways to branch to the individual routine once the
integer value representing the interrupt level is loaded into GPR4. For
example, a table of interrupt handler addresses could be constructed,
and GPR3 could be used to index into that table, get the appropriate
interrupt handler address for a level, and branch to that address.
Perform Handler
Functions
Once in the handler, one approach would be to do all the interrupt
handler functions and then leave. But since interrupts are still disabled,
this would result in the longest interrupt latency. A popular approach is
to use a multitasking kernel operating system which would send
appropriate messages or flags and then exit.
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