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參數(shù)資料
| 型號(hào)： | MPC2107SG15 |
| 廠商： | MOTOROLA INC |
| 元件分類： | SRAM |
| 英文描述： | 256KB and 512KB BurstRAM Secondary Cache Modules for PowerPC PReP/CHRP Platforms |
| 中文描述： | 32K X 64 CACHE SRAM MODULE, 15 ns, PDMA182 |
| 文件頁數(shù)： | 9/24頁 |
| 文件大?。?/td> | 228K |
| 代理商： | MPC2107SG15 |
MPC2104
MPC2105
MPC2106
MPC2107
9
MOTOROLA FAST SRAM
DATA RAMs AC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V
±
5% TA = 0 to + 70
°
C, Unless Otherwise Noted)
Input Timing Measurement Reference Level
Input Pulse Levels
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Rise/Fall Time
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5 V
. . . . . . . . . . . . . . .
0 to 3.0 V
3 ns
Output Timing Reference Level
Output Load
. . . . . . . . . . . .
1.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . .
See Figure 1A Unless Otherwise Noted
SYNCHRONOUS DATA RAMs READ/WRITE CYCLE TIMING
(See Notes 1, 2, 3, and 7)
MPC2104
MPC2105
MPC2106
Parameter
Symbol
Min
Max
Unit
Notes
Cycle Time
tKHKH
tKHQV
tGLQV
tKHQX1
tKHQX2
tGLQX
tGHQZ
tKHQZ
tKHKL
tKLKH
tAVKH
tSVKH
tDVKH
tWVKH
tBAVVKH
tEVKH
15
—
ns
Clock Access Time
—
9
ns
4
Output Enable to Output Valid
—
5
ns
Clock High to Output Active
6
—
ns
Clock High to Output Change
3
—
ns
Output Enable to Output Active
0
—
ns
Output Disable to Q High–Z
2
6
ns
Clock High to Q High–Z
—
6
ns
Clock High Pulse Width
5
—
ns
Clock Low Pulse Width
5
—
ns
Setup Time
Address
7.5
—
ns
5, 6
Setup Times:
Address Status
Data In
Write
Address Advance
Chip Enable
2.5
—
ns
5
Hold Times:
Address
Address Status
Data In
Write
Address Advance
Chip Enable
tKHAX
tKHTSX
tKHDX
tKHWX
tKHBAX
tKHEX
0.5
—
ns
5
NOTES:
1. In setup and hold times, W (write) refers to either one or both byte write enables LW and UW.
2. All read and write cycle timings are referenced from CLK or COE.
3. COE is a don’t care when UW or LW is sampled low.
4. Maximum access times are guaranteed for all possible PowerPC external bus cycles.
5. This is a synchronous device. All addresses must meet the specified setup and hold times for
ALL
rising edges of CLK whenever TSP or
TSC is low, and the chip is selected. All other synchronous inputs must meet the specified setup and hold times for
ALL
rising edges of
CLK when the chip is enabled. Chip enable must be valid at each rising edge of clock for the device (when TSP or TSC is low) to remain
enabled.
6. 5 ns of set–up delay is incurred in address buffers.
7. Applies to MPC2104, MPC2105, and MPC2106.
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