參數(shù)資料
型號(hào)： MPC2107SG15
廠商： MOTOROLA INC
元件分類： SRAM
英文描述： 256KB and 512KB BurstRAM Secondary Cache Modules for PowerPC PReP/CHRP Platforms
中文描述： 32K X 64 CACHE SRAM MODULE, 15 ns, PDMA182
文件頁(yè)數(shù)： 6/24頁(yè)
文件大?。?/td> 228K
代理商： MPC2107SG15
MPC2104
MPC2105
MPC2106
MPC2107
6
MOTOROLA FAST SRAM
PIN DESCRIPTIONS
Pin Locations
Symbol
Type
Description
68, 69, 70, 71, 73, 74, 75, 76,
78, 79, 80, 82, 83, 84, 85,
159, 160, 161, 162, 164, 165,
166, 167, 169, 170, 171, 173,
174, 175
A0 – A28
Input
Address Inputs – (MSB:0, LSB:28)
62
ADDR0
Input
Least significant address bit when asynchronous Data RAMs are used.
153
ADDR1
Input
Next to least significant address bit when asynchronous Data RAMs are used.
30, 56, 117, 146, 148
CLK0 – CLK4
Input
Clock Inputs – CLK2 is for Tag RAM, CLK0, 1, 3, and 4 are for Data RAMs only.
For MPC2106 use all the clocks. For MPC2104 or MPC2105 use CLK0–CLK2
only. For MPC2107 use CLK2 only.
4, 5, 6, 7, 10, 11, 12, 14, 16,
17, 19, 20, 22, 24, 25, 26, 27,
95, 96, 97, 98, 101, 102, 103,
105, 107, 108, 110, 111, 113,
115, 119
DH0 – DH31
I/O
High Data Bus – (MSB:0, LSB:31)
32, 33, 34, 37, 38, 39, 40, 43,
44, 45, 47, 49, 50, 52, 53, 54,
121, 122, 124, 125, 126, 129,
130, 131, 133, 135, 136, 138,
139, 141, 143, 144
DL0 – DL31
I/O
Low Data Bus – (MSB:0, LSB:31)
9, 15, 21, 28, 35, 42, 48, 58
DP0 – DP7
I/O
Data Parity Bits – (MSB:0, LSB:7)
3, 94
PD2, PD3
Output
Presence detect bits.
2
PD0/IDSCLK
Input
Presence detect bit 0/EEPROM serial clock. (EEPROM option only.)
93
PD1/IDSDATA
I/O
Presence detect bit 1/EEPROM serial data. (EEPROM option only.)
64, 65
ADS0, ADS1
Input
Data RAM Address Strobe – For MPC2104 or MPC2105 use ADS0 only. For
MPC2106 use ADS0, ADS1.
151
ALE
Input
Data RAM Address Latch Enable – Use for asynchronous Data RAM only.
155, 156
CNTEN0,
CNTEN1
Input
Data RAM Count Enables – For MPC2104 or MPC2105 use CNTEN0 only. For
MPC2106 use CNTEN0, CNTEN1.
59, 60
COE0,
COE1
Input
Data RAM Output Enables – For MPC2104 or MPC2105 use COE0 only. For
all others use COE0, COE1.
100, 106, 112, 120,
128, 134, 140, 150
CWE0 – CWE7
Input
Data RAM Write Enables – (MSB:0, LSB:7)
87
TCLR
Input
Tag RAM clear.
88
MATCH
Output
Tag RAM active high match indication.
178
VALIDIN
Input
Tag RAM valid bit.
179
TWE
Input
Tag RAM write enable.
89
TOE
Input
Tag RAM output enable.
90
DIRTYIN
Input
Dirty input bit.
181
DIRTYOUT
Output
Dirty output bit.
180
STANDBY
Input
Standby pin. Reduces standby power consumption.
176, 63, 154
RESERVED
Reserved pin.
8, 23, 51, 61, 77, 99, 114,
142, 152, 168
VCC3
Input
+ 3.3 V power supply. Must be connected.
18, 36, 66, 67, 86, 109, 127,
157, 158, 177
VCC5
Input
+ 5 V power supply. Must be connected.
1, 13, 29, 31, 41, 46, 55, 57,
72, 81, 91, 92, 104, 116,
118, 123, 132, 137, 145,
147, 149, 163, 172, 182
VSS
Input
Ground
176
BURSTMODE
Input
Burstmode. 0 = Linear, 1 = Interleaved.
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