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參數(shù)資料
| 型號： | MPC2107SG15 |
| 廠商： | MOTOROLA INC |
| 元件分類： | SRAM |
| 英文描述： | 256KB and 512KB BurstRAM Secondary Cache Modules for PowerPC PReP/CHRP Platforms |
| 中文描述： | 32K X 64 CACHE SRAM MODULE, 15 ns, PDMA182 |
| 文件頁數(shù)： | 14/24頁 |
| 文件大?。?/td> | 228K |
| 代理商： | MPC2107SG15 |
MPC2104
MPC2105
MPC2106
MPC2107
14
MOTOROLA FAST SRAM
ASYNCHRONOUS DATA RAMs WRITE CYCLE 1
(See Notes 1 and 2)
MPC2107–15
Parameter
Symbol
Min
Max
Unit
Notes
Write Cycle Time
tAVAV
tAVWL
tAVWH
tWLWH
tWLEH
15
—
ns
3
Address Set–up Time
0
—
ns
Address Valid to End of Write
12
—
ns
Write Pulse Width
12
—
ns
Write Pulse Width, G High
tWLWH
tWLEH
10
—
ns
4
Data Valid to End of Write
tDVWH
tWHDX
tWLQZ
tWHQX
tWHAX
7
—
ns
Data Hold Time
0
—
ns
Write Low to Output High–Z
0
7
ns
5,6,7
Write High to Output Active
5
—
ns
5,6,7
Write Recovery Time
0
—
ns
NOTES:
1. A write occurs during the overlap of E low and W low.
2. If E goes low coincident with or after W goes low, the output will remain in a high impedance state.
3. All timings are referenced from the last valid address to the first transitioning address.
4. If E
≥
VIH, the output will remain in a high impedance state.
5. At any given voltage and temperature, tWLQZ (max) is less than tWHQX (min), both for a given device and from device to device.
6. Transition is measured
±
500 mV from steady–state voltage with load of Figure 1B.
7. This parameter is sampled and not 100% tested.
ASYNCHRONOUS WRITE CYCLE 1 (W Controlled, See Notes 1 and 2)
DATA VALID
tDVWH
tAVWL
tAVWH
tAVAV
tWHAX
tWLWH
tWHDX
tWLQZ
tWHQX
HIGH–Z
HIGH–Z
A (ADDRESS)
W (WRITE ENABLE)
E (CHIP ENABLE)
Q (DATA OUT)
D (DATA IN)
tWLEH
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