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參數(shù)資料
| 型號(hào)： | MPC2107SG15 |
| 廠商： | MOTOROLA INC |
| 元件分類： | SRAM |
| 英文描述： | 256KB and 512KB BurstRAM Secondary Cache Modules for PowerPC PReP/CHRP Platforms |
| 中文描述： | 32K X 64 CACHE SRAM MODULE, 15 ns, PDMA182 |
| 文件頁(yè)數(shù)： | 12/24頁(yè) |
| 文件大?。?/td> | 228K |
| 代理商： | MPC2107SG15 |
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MPC2104
MPC2105
MPC2106
MPC2107
12
MOTOROLA FAST SRAM
AC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V
±
5% TA = 0 to + 70
°
C, Unless Otherwise Noted)
Input Timing Measurement Reference Level
Input Pulse Levels
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Rise/Fall Time
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5 V
. . . . . . . . . . . . . . .
0 to 3.0 V
3 ns
Output Timing Reference Level
Output Load
. . . . . . . . . . . .
1.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . .
See Figure 1A Unless Otherwise Noted
ASYNCHRONOUS DATA RAMs READ CYCLE TIMING
(See Notes 1 and 8)
MPC2107–15
Parameter
Symbol
Min
Max
Unit
Notes
Cycle Time
tAVAV
tAVQV
tELQV
tGLQV
tAXQX
tELQX
tEHQZ
tGLQX
tGHQZ
tELICCH
tEHICCL
15
—
ns
2
Address Access Time
—
15
ns
Enable Access Time
—
15
ns
3
Output Enable Access Time
—
8
ns
Output Hold from Address Change
4
—
ns
4, 5, 6
Enable Low to Output Active
4
—
ns
4, 5, 6
Enable High to Output High–Z
0
8
ns
4, 5, 6
Output Enable Low to Output Active
0
—
ns
4, 5, 6
Output Enable High to Output High–Z
0
7
ns
4, 5, 6
Power Up Time
0
—
ns
Power Down Time
—
15
ns
NOTES:
1. W is high for read cycle.
2. All timings are referenced from the last valid address to the first transitioning address.
3. Addresses valid prior to or coincident with E going low.
4. At any given voltage and temperature, tEHQZ(max) is less than tELQX(min), and tGHQZ(max) is less than tGLQX(min), both for a given device
and from device to device.
5. Transition is measured
±
500 mV from steady–state voltage with load of Figure 1B.
6. This parameter is sampled and not 100% tested.
7. Device is continuously selected (E = VIL, COE0 = VIL).
8. Applies to MPC2107.
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