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參數(shù)資料
| 型號： | MPC2104P |
| 廠商： | Motorola, Inc. |
| 英文描述： | 256KB/512KB BurstRAM Secondary Cache Modules for PowerPC PReP/CHRP Platforms |
| 中文描述： | 256KB/512KB BurstRAM二級緩存模塊為PowerPC制備/ CH旺平臺 |
| 文件頁數(shù)： | 7/16頁 |
| 文件大?。?/td> | 158K |
| 代理商： | MPC2104P |
MPC2104P
MPC2105P
7
MOTOROLA FAST SRAM
ABSOLUTE MAXIMUM RATINGS
(Voltages Referenced to VSS = 0 V)
Rating
Symbol
Value
Unit
Power Supply Voltage
Tag
Data RAM
VCC
VDD
– 0.5 to + 7.0
– 0.5 to + 4.6
V
Voltage Relative to VSS
Tag
Data RAM
Vin, Vout
– 0.5 to VCC + 0.5
– 0.5 to VDD + 0.5
V
Output Current (per I/O)
Tag
Data RAM
Iout
±
20
±
30
mA
Power Dissipation
PD
Tbias
TA
Tstg
3.86
W
Temperature Under Bias
– 10 to + 85
°
C
Operating Temperature
0 to +70
°
C
Storage Temperature
NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED OPER-
ATING CONDITIONS. Exposure to higher than recommended voltages for
extended periods of time could affect device reliability.
– 55 to + 125
°
C
DC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V
±
5%, VDD = 3.3 V + 10%, – 5%, TA = 0 to + 70
°
C, Unless Otherwise Noted)
RECOMMENDED OPERATING CONDITIONS
(Voltages Referenced to VSS = 0 V)
Parameter
Symbol
Min
Max
Unit
Supply Voltage (Operating Voltage Range)
VCC
VDD
4.75
3.135
5.25
3.60
V
Input High Voltage
VIH
VIL
2.2
VDD + 0.3**
0.8
V
Input Low Voltage
*VIL (min) = – 0.5 V dc; VIL (min) = – 2.0 V ac (pulse width
≤
20 ns) for I
≤
20.0 mA.
**VIH (max) = VDD + 0.3 V dc; VIH (max) = VDD + 2.0 V ac (pulse width
≤
20 ns) for I
≤
20.0 mA.
– 0.5*
V
DC CHARACTERISTICS
Parameter
Symbol
Min
Max
Unit
Input Leakage Current (All Inputs, Vin = 0 to VDD)
Output Leakage Current (CG = VIH, Vout = 0 to VDD)
TTL Output Low Voltage (IOL = + 8.0 mA)
TTL Output High Voltage (IOH = – 4.0 mA)
Ilkg(I)
Ilkg(O)
VOL
VOH
—
±
1.0
μ
A
—
±
1.0
μ
A
—
0.4
V
2.4
—
V
POWER SUPPLY CURRENTS
Parameter
Symbol
Max
Unit
AC Supply Current (CG = VIH, E = VIL, Iout = 0 mA, All Inputs = VIL and VIH, MPC2104P
VIL = 0.0 V and VIH
≥
3.0 V, Cycle Time
≥
20 ns) MPC2105P
IDDA
410
700
mA
ICCA
320
mA
AC Standby Current (E = VIH, Iout = 0 mA, All Inputs = VIL or VIH MPC2104P
VIL = 0.0 V and VIH
≥
3.0 V, Cycle Time
≥
20 ns) MPC2105P
ISB1 (VDD)
210
240
mA
ISB1 (VCC)
320
mA
CAPACITANCE
(f = 1.0 MHz, dV = 3.0 V, TA = 25
°
C, Periodically Sampled Rather Than 100% Tested)
Parameter
Symbol
Max
Unit
Input Capacitance
(A13 – A28)
(Data RAM Control Pins)
(CLK0 – CLK2)
(Tag Control Pins)
Cin
15
10
5
5
pF
Tag Output Capacitance
(MATCH, DIRTYOUT)
Cout
CI/O
CI/O
7
pF
Data RAM Input/Output Capacitance
(DH0 – DH31, DL0 – DL31)
8
pF
Tag Input/Output Capacitance
(A0 – A11)
7
pF
This device contains circuitry to protect the
inputs against damage due to high static volt-
ages or electric fields; however, it is advised
that normal precautions be taken to avoid
application of any voltage higher than maxi-
mum rated voltages to this high–impedance
circuit.
This BiCMOS memory circuit has been
designed to meet the dc and ac specifications
shown in the tables, after thermal equilibrium
has been established.
This device contains circuitry that will ensure
the output devices are in High–Z at power up.
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