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參數(shù)資料
| 型號： | MPC107 |
| 廠商： | Motorola, Inc. |
| 英文描述： | 32-Bit Microprocessor(32位微處理器) |
| 中文描述： | 32位微處理器（32位微處理器） |
| 文件頁數(shù)： | 17/46頁 |
| 文件大?。?/td> | 585K |
| 代理商： | MPC107 |
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MPC107 Hardware Specifications (Rev 0.2)
PRELIMINARYSUBJECT TO CHANGE WITHOUT NOTICE
17
Electrical and Thermal Characteristics
1.4.3.2 Input AC Timing SpeciTcations
Table 9 provides the input AC timing speciTcations. See Figure 7 and Figure 8.
Notes:
1
All memory, processor, and related interface input signal speciTcations are measured from the TTL level (0.8
or 2.0 V) of the signal in question to the V
= 1.4 V of the rising edge of the memory bus clock,
SDRAM_SYNC_IN. SDRAM_SYNC_IN is the same as PCI_SYNC_IN in 1:1 mode, but is twice the fre-
quency in 2:1 mode (processor/memory bus clock rising edges occur on every rising and falling edge of
PCI_SYNC_IN). See Figure 7.
All PCI signals are measured from OVdd/2 of the rising edge of PCI_SYNC_IN to 0.4*OVdd of the signal in
question for 3.3 V PCI signaling levels. See Figure 8.
Input timings are measured at the pin.
t
CLK
is the time of one SDRAM_SYNC_IN clock cycle.
All mode select input signals speciTcations are measured from the TTL level (0.8 or 2.0 V) of the signal in
question to the V
M
= 1.4 V of the rising edge of the HRESET signal. See Figure 9.
1
2
3
4
Table 9. Input AC Timing Specifications
At recommended operating conditions (See Table 2) with GVdd = 3.3 V ± 5% and LVdd = 3.3 V ± 5%
Num
Characteristic
Min
Max
Units
Notes
10a
PCI Input Signals Valid to PCI_SYNC_IN (Input Setup)
2.0
ns
2,3
10b
Memory Interface Signals
Valid to SDRAM_SYNC_IN (Input Setup)
2.0
ns
1,3
10c
Epic, Misc. Debug Input Signals Valid to SDRAM_SYNC_IN
(Input Setup)
2.0
ns
1,3
10d
I
2
C Input Signals Valid to SDRAM_SYNC_IN (Input Setup)
2.0
ns
1,3
10e
Mode select Inputs Valid to HRESET (Input Setup)
9*t
CLK
ns
1,3D5
10f
60x Processor Interface Signals
Valid to SDRAM_SYNC_IN (Input Setup)
2.0
ns
1,3
11a1
PCI_SYNC_IN (SDRAM_SYNC_IN) to Inputs Invalid (Input Hold)
1.0
ns
2,3
11a2
Memory Interface Signals
SDRAM_SYNC_IN to Inputs Invalid (Input Hold)
0.5
ns
1,3
11a3
60x Processor Interface Signals
SDRAM_SYNC_IN to Inputs Invalid (Input Hold)
0
ns
1,3
11b
HRESET to Mode select Inputs Invalid (Input Hold)
0
ns
1,3,5
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