參數(shù)資料
型號(hào): MM908E622ACDWB/R2
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PDSO54
封裝: 17.90 X 7.50 MM, 0.65 MM PITCH, PLASTIC, SOIC-54
文件頁數(shù): 47/66頁
文件大?。?/td> 1277K
代理商: MM908E622ACDWB/R2
Analog Integrated Circuit Device Data
Freescale Semiconductor
51
908E622
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
Analog Die System Trim Values
For improved application performance, and to ensure the
outlined datasheet values, the analog die needs to be
trimmed. For this purpose, 3 trim values are stored in the
Flash memory at addresses $FDC4 - $FDC6. These values
have to be copied into the analog die SPI registers:
copy $FDC4 into SYSTRIM1 register $0F
copy $FDC5 into SYSTRIM2 register $10
copy $FDC6 into SYSTRIM3 register $11
Note: These values have to be copied to the respective
SPI register after a reset, to ensure proper trimming of the
device.
System Test Register (SYSTEST)
The System Test Register is reserved for production
testing and is not allowed to be written into.
System Trim Register 1 (SYSTRIM1)
HVDDT1:0 - HVDD Over-current Shutdown Delay Bits
These read/write bits allow changing the filter time (for
capacitive load) for the HVDD over-current detection.
Reset clears the HVDDT1:0 bits an sets the delay to the
maximum value.
Table 15. HVDD Over-current Shutdown Selection Bits
ITRIM3:0 - IRef Trim Bits
These write only bits are for trimming the internal current
references IRef (also A0, A0CST). The provided trim
values have to be copied into these bits after every reset.
Reset clears the ITRIM3:0 bits.
1
00
92
124
ms
62
92
ms
77
ms
±19.5%
01
46
62
31
46
38.5
10
23
31
15.5
23
19.25
11
11.5
15.5
7.75
11.5
9.625
2
00
52
68
ms
34
52
ms
43
ms
±20.9%
01
26
34
17
26
21.5
10
13
17
8.5
13
10.75
11
6.5
8.5
4.25
6.5
5.375
Table 14. Window Clear Interval
Window
Range
Period
Select bits
Watchdog Period
t_wd
Effective Open Window
Optimal Clear Interval
Register Name and Address: SYSTEST - $0E
Bit7
6
5
4
3
2
1
Bit0
Read
reser
ved
reser
ved
reser
ved
reser
ved
reser
ved
reser
ved
reser
ved
reser
ved
Write
Reset
0
Note: do not write to the reserved bits
Register Name and Address: IBIAS - $0F
Bit7
6
5
4
3
2
1
Bit0
Read
HVD
DT1
HVD
DT0
0
reser
ved
0
reser
ved
ITRI
M3
ITRI
M2
ITRI
M1
ITRI
M0
Write
Reset
0
Note: do not change (set) the reserved bits
HVDDT1
HVDDT0
typical Delay
00
950
μs
01
536
μs
10
234
μs
11
78
μs
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