參數(shù)資料
型號: MM908E622ACDWB/R2
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PDSO54
封裝: 17.90 X 7.50 MM, 0.65 MM PITCH, PLASTIC, SOIC-54
文件頁數(shù): 21/66頁
文件大小: 1277K
代理商: MM908E622ACDWB/R2
Analog Integrated Circuit Device Data
28
Freescale Semiconductor
908E622
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
HO Input Interrupt
The H0 interrupt flag H0IF is set in run mode by a state
change of the H0F flag (rising or falling edge on the enabled
input). The interrupt function is available if the input is
selected as General Purpose, or as 2pin Hall sensor input.
The interrupt is maskable with the H0IE bit in the Interrupt
Mask Register.
During Stop and Sleep mode the H0I circuitry is disabled.
L0 input Interrupt
The L0 interrupt flag L0IF is set in run mode by a state
change of the L0F flag (rising or falling edge). The interrupt is
maskable with the L0IE bit in the interrupt mask register.
INTERRUPT FLAG REGISTER (IFR)
L0IF - L0 Input Flag Bit
This read/write flag is set on a falling or rising edge at the
L0 input. Clear L0IF by writing a logic [1] to L0IF. Reset clears
the L0IF bit. Writing a logic [0] to L0IF has no effect.
1 = rising or falling edge on L0 input detected
0 = no state change on L0 input detected
H0IF - H0 Input Flag Bit
This read/write flag is set on a falling or rising edge at the
H0 input. Clear H0IF by writing a logic [1] to H0IF. Reset
clears the H0IF bit. Writing a logic [0] to H0IF has no effect.
1 = state change on the hallflags detected
0 = no state change on the hallflags detected
LINIF - LIN Flag Bit
This read/write flag is set if a rising edge is detected and
the bus was dominant longer than TpropWL. Clear LINIF by
writing a logic [1] to LINIF. Reset clears the LINIF bit. Writing
a logic [0] to LINIF has no effect.
1 = LIN bus interrupt has occurred
0 = not LIN bus interrupt occurred since last clear
HTIF - High Temperature Flag Bit
This read/write flag is set on high temperature condition.
Clear HTIF by writing a logic [1] to HTIF. If a high temperature
condition is still present while writing a logical one to HTIF,
the writing has no effect. Therefore, a high temperature
interrupt cannot be lost due to an inadvertent clearing of
HTIF. Reset clears the HTIF bit. Writing a logic [0] to HTIF
has no effect.
1 = high temperature condition has occurred
0 = high temperature condition has not occurred
LVIF - Low Voltage Flag Bit
This read/write flag is set on low voltage condition. Clear
LVIF by writing a logic [1] to LVIF. If a low voltage condition
is still present while writing a logical one to LVIF, writing has
no effect. Therefore, a low voltage interrupt cannot be lost
due to inadvertent clearing of LVIF. Reset clears the LVIF bit.
Writing a logic [0] to LVIF has no effect.
1 = low voltage condition has occurred
0 = low voltage condition has not occurred
HVIF - High Voltage Flag Bit
This read/write flag is set on a high voltage condition.
Clear HVIF by writing a logic [1] to HVIF. If a high voltage
condition is still present while writing a logical one to HVIF,
the writing has no effect. Therefore, a high voltage interrupt
cannot be lost due to an inadvertent clearing of HVIF. Reset
clears the HVIF bit. Writing a logic [0] to HVIF has no effect.
1 = high voltage condition has occurred
0 = high voltage condition has not occurred
PSFIF - Power Stage Fail Bit
This read-only flag is set on a fail condition on one of the
power outputs (HBx, HSx, HVDD, EC, H0). Reset clears the
PSFIF bit. Clear this flag, by writing a logic [1] to the
appropriate fail flag.
1 = power stage fail condition has occurred
0 = power stage fail condition has not occurred
Figure 14. Principal Implementation of the PSFIF
Register Name and Address: IFR - $0A
Bit7
6
5
4
3
2
1
Bit0
Read
L0IF
H0IF
LINIF
0
HTIF
LVIF
HVIF
PSFIF
Write
Reset
0
ECOCF
ECOLF
HS3OC
HS2OC
HS1OC
HB4OC
HB3OC
HB2OC
HB1OC
HVDDOCF
H0OCF
HBFF
HSFF
HVDDOCF
ECFF
H0OCF
PSFIF
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