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參數(shù)資料
| 型號： | MM908E622ACDWB/R2 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PDSO54 |
| 封裝： | 17.90 X 7.50 MM, 0.65 MM PITCH, PLASTIC, SOIC-54 |
| 文件頁數(shù)： | 42/66頁 |
| 文件大?。?/td> | 1277K |
| 代理商： | MM908E622ACDWB/R2 |
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Analog Integrated Circuit Device Data
Freescale Semiconductor
47
908E622
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
MCU. The on-chip regulator consist of two elements, the
main regulator, and the low voltage reset circuit.
The VDD regulator accepts an unregulated input supply
and provides a regulated VDD supply to all digital sections of
the device. The output of the regulator is also connected to
the VDD pin to provide the 5.0V to the microcontroller.
Run Mode
During RUN mode, the main voltage regulator is on. It will
provide a regulated supply to all digital sections.
STOP Mode
During STOP mode, the Stop mode regulator will take care
of suppling a regulated output voltage. The Stop mode
regulator has a limited output current capability.
SLEEP Mode
In Sleep mode, the main voltage regulator external VDD is
turned off and the LVR circuitry will force the RST_A pin low.
LOGIC COMMANDS AND REGISTERS
908E622 SERIAL PHERIPHERAL INTERFACE (SPI)
The Serial Peripheral Interface (SPI) creates the
communication link between the MCU and the analog die.
The interface consists of four pins
MOSI - Master Out Slave In (internal pulldown)
MISO - Master In Slave Out
SPSCK - Serial Clock (internal pulldown)
SS - Slave Select (internal pullup)
A complete data transfer via the SPI, consists of 2 bytes.
The master sends address and data, the slave returns
system status and the data of the selected address.
Figure 31. SPI Protocol
During the inactive phase of SS, the new data transfer will
be prepared. The falling edge on the SS line, indicates the
start of a new data transfer (framing) and puts MISO in the
low impedance mode. The first valid data is moved to
MISO with the rising edge of SPSCK.
The MOSI and MISO will change data on a rising edge of
SPSCK.
The MOSI and MISO will be sampled on a falling edge of
SPSCK.
The data transfer is only valid, if exactly 16 sample clock
edges are present in the active phase of SS.
After a write operation the transmitted data will be latched
into the register, by the rising edge of SS.
Register read data is internally latched into the SPI, at the
time when the parity bit is transferred
SS high will force MISO to a high impedance
Master Address Byte
A4 - A0
includes the address of the desired register.
S7
S6
S5
S4
S3
S2
S1
S0
R/W
A4
A3
A2
A1
A0
P
X
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
System Status Register
Read/Write, Address, Parity
Data (Register write)
Data (Register read)
Rising edge of SPSCK
Change MISO/MOSI
Output
Falling edge of SPSCK
Sample MISO/MOSI
Input
Slave latch
register address
Slave latch
data
SS
MOSI
MISO
SPSCK
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MM908E622ACEK | 功能描述:8位微控制器 -MCU QUAD H-B TRIHS EC GLASS RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| MM908E622ACPEK | 功能描述:IC QUAD HALF BRDG TRPL SW 54SOIC RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微控制器 - 特定應(yīng)用 系列:- 產(chǎn)品變化通告:Product Discontinuation 26/Aug/2009 標(biāo)準(zhǔn)包裝:250 系列:- 應(yīng)用:網(wǎng)絡(luò)處理器 核心處理器:4Kc 程序存儲器類型:- 控制器系列:- RAM 容量:16K x 8 接口:以太網(wǎng)，UART，USB 輸入/輸出數(shù):- 電源電壓:1.8V, 3.3V 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:208-LQFP 包裝:帶卷 (TR) 供應(yīng)商設(shè)備封裝:PG-LQFP-208 其它名稱:SP000314382 |
| MM908E622ACPEKR2 | 功能描述:8位微控制器 -MCU QUAD H-B, TRIHS, EC RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| MM908E624 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:TRIPLE HIGH-SIDE SWITCH WITH EMBEDDED MCU AND LIN |
| MM908E624ACDWB | 功能描述:IC TRPL SWITCH MCU/LIN 54-SOIC RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微控制器 - 特定應(yīng)用 系列:- 產(chǎn)品變化通告:Product Discontinuation 26/Aug/2009 標(biāo)準(zhǔn)包裝:250 系列:- 應(yīng)用:網(wǎng)絡(luò)處理器 核心處理器:4Kc 程序存儲器類型:- 控制器系列:- RAM 容量:16K x 8 接口:以太網(wǎng)，UART，USB 輸入/輸出數(shù):- 電源電壓:1.8V, 3.3V 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:208-LQFP 包裝:帶卷 (TR) 供應(yīng)商設(shè)備封裝:PG-LQFP-208 其它名稱:SP000314382 |
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