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參數(shù)資料
| 型號(hào)： | MM908E621ACDWB/R2 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PDSO54 |
| 封裝： | 17.90 X 7.50 MM, 0.65 MM PITCH, PLASTIC, SOIC-54 |
| 文件頁數(shù)： | 7/65頁 |
| 文件大小： | 1221K |
| 代理商： | MM908E621ACDWB/R2 |
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Analog Integrated Circuit Device Data
Freescale Semiconductor
15
908E621
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics
All characteristics are for the analog chip only. Please refer to the 68HC908EY16 datasheet for characteristics of the
microcontroller chip. Characteristics noted under conditions 9.0V ≤ VSUP ≤ 16V, -40°C ≤ TJ ≤ 125°C, unless otherwise noted.
Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
LIN PHYSICAL LAYER
Dominant Propagation Delay TXD to LIN
tDOM-MIN
——
50
μs
Dominant Propagation Delay TXD to LIN
tDOM-MAX
——
50
μs
Recessive Propagation Delay TXD to LIN
tREC-MIN
——
50
μs
Recessive Propagation Delay TXD to LIN
tREC-MAX
——
50
μs
Duty Cycle 1: D1 = tBUS_REC(MIN) / (2 x tBIT), tBIT = 50μs, VSUP = 7.0V…18V
D1
0.396
–
Duty Cycle 2: D2 = tBUS_REC(MAX) / (2 x tBIT), tBIT = 50μs, VSUP = 7.6V…18V
D2
–
0.581
Driver Characteristics for Slow Slew Rate(25), (27)
Dominant Propagation Delay TXD to LIN
tDOM-MIN
—
100
μs
Dominant Propagation Delay TXD to LIN
tDOM-MAX
—
100
μs
Recessive Propagation Delay TXD to LIN
tREC-MIN
—
100
μs
Recessive Propagation Delay TXD to LIN
tREC-MAX
—
100
μs
Duty Cycle 3: D3 = tBUS_REC(MIN) / (2 x tBIT), tBIT = 96μs, VSUP = 7.0V…18V
D3
0.417
–
Duty Cycle4: D4 = tBUS_REC(MAX) / (2 x tBIT), tBIT = 96μs, VSUP = 7.6V…18V
D4
–
0.590
Driver Characteristics for Fast Slew Rate
LIN High Slew Rate (Programming Mode)
SRFAST
—20
—
V/
μs
Receiver Characteristics and Wake-up Timings
Receiver Dominant Propagation Delay(28)
tRL
—3.5
6.0
μs
Receiver Recessive Propagation Delay(28)
tRH
—3.5
6.0
μs
Receiver Propagation Delay Symmetry
tR-SYM
-2.0
—
2.0
μs
Bus Wake-up Deglitcher
tPROPWL
30
50
150
μs
Bus Wake-up Event Reported(29)
tWAKE
—20
—
μs
Notes
25.
VSUP from 7.0V to 18V, bus load R0 and C0 1.0nF/1.0kΩ, 6.8nF/660Ω, 10nF/500Ω. Measurement thresholds: 50% of TXD signal to
LIN signal threshold defined at each parameter.
26.
27.
28.
Measured between LIN signal threshold VIL or VIH and 50% of RXD signal.
29.
tWAKE is typically 2 internal clock cycles after LIN rising edge detected. See Figure 9 and Figure 8, page 19. In Sleep mode the VDD
rise time is strongly dependent upon the decoupling capacitor at VDD pin.
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