- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄98023 > MM908E621ACDWB/R2 (FREESCALE SEMICONDUCTOR INC) 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PDSO54 PDF資料下載
參數(shù)資料
| 型號： | MM908E621ACDWB/R2 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PDSO54 |
| 封裝： | 17.90 X 7.50 MM, 0.65 MM PITCH, PLASTIC, SOIC-54 |
| 文件頁數(shù)： | 26/65頁 |
| 文件大?。?/td> | 1221K |
| 代理商： | MM908E621ACDWB/R2 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁當(dāng)前第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁
Analog Integrated Circuit Device Data
32
Freescale Semiconductor
908E621
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
POR— Power On Reset bit
This read/write bit is set after power on. Bit is cleared by
writing a logic “1” to this location.
1 = Reset due to power on
0 = no power on reset
PINR— Reset Forced from External Reset Pin Bit
This read/write bit is set after a reset was forced on the
external reset RST_A pin. The bit is cleared by writing an
logic “1” to this location.
1 = reset source is external reset pin
0 = no external reset
WDR— Watch Dog Reset Bit
This read/write flag is set due to a watchdog timeout or
wrong watchdog timer reset. Clear WDR by writing a logic “1”
to WDR.
1 = reset source is watchdog
0 = no watchdog reset
HTR— High Temperature Reset Bit
This read/write bit is set if the chip temperature exceeds a
certain value. The bit is cleared by writing a logic “1” to this
location.
1 = reset due to high temperature condition
0 = no high temperature reset
LVR— Low Voltage Reset Bit
This read/write bit is set if the external VDD voltage coming
from the main voltage regulator falls below a certain value.
The bit is cleared by writing a logic “1” to this location.
1 = reset due to low voltage condition
0 = no low voltage reset
LINWF— LIN Wake-up Flag
This read/write bit is set if a bus activity was the case of an
wake-up. The bit is cleared by writing a logic “1” to this
location.
1 = Wake-up due to bus activity
0 = no wake-up due to bus activity
L0WF— L0 Wake-up Flag
This read/write bit is set if a event on the L0 pin caused an
wake-up. The bit is cleared by writing a logic “1” to this
location.
1 = Wake-up due to L0 pin
0 = no Wake-up due to L0 pin
ANALOG DIE INPUTS/OUTPUTS
LIN PHYSICAL LAYER
The LIN bus pin provides a physical layer for single wire
communication in automotive applications. The LIN physical
layer is designed to meet the LIN physical layer specification.
The LIN driver is a low side MOSFET with internal current
limitation and thermal shutdown. An internal pullup resistor
with a serial diode structure is integrated, so no external
pullup components are required for the application in a slave
node. The fall time from dominant to recessive and the rise
time from recessive to dominant is controlled. The symmetry
between both slew rate controls is guaranteed.
The slew rate can be selected for optimized operation at
10 and 20kBit/s as well as high baud rates for test and
programming. The slew rate can be adapted with 2 bits
SRS[1:0] in the System Control Register. The initial slew rate
is optimized for 20kBit/s.
The LIN pin offers high susceptibility immunity level from
external disturbance, guaranteeing communication during
external disturbance.
The LIN transmitter circuitry is enabled by setting the
PSON bit in the System Control Register (SYSCTL).
If the transmitter works in the current limitation region, the
LINCL bit in the System Status Register (SYSSTAT) is set
and the LIN transceiver is disabled after a certain time.
For improved performance and safe behavior, in case of
LIN bus short to Ground or LIN bus leakage during low power
mode, the internal pullup resistor on the LIN pin is
disconnected from VSUP and a small current source keeps
the LIN bus at recessive level. In case of a LIN bus short to
GND, this feature will reduce the current consumption in
STOP and SLEEP modes.
Register Name and Address: RSR - $0D
Bit7
6
5
4
3
2
1
Bit0
Read
POR
PINR
WDR
HTR
LVR
0
LINWF LOWF
Write
POR
1
0
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MM908E621ACDWB | 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PDSO54 |
| MM908E622ACDWB/R2 | 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PDSO54 |
| MM908E624ACDWB/R | 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PDSO54 |
| MM908E625ACDWB | 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PDSO54 |
| MMBD1010LT3 | 0.2 A, 2 ELEMENT, SILICON, SIGNAL DIODE, TO-236AB |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MM908E621ACPEK | 功能描述:8位微控制器 -MCU QUAD H-B/3-HS W/MCU & LI RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| MM908E621ACPEKR2 | 功能描述:8位微控制器 -MCU QUAD HB AND TRIPLE HS RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| MM908E622 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Integrated Quad Half-Bridge, Triple High-Side and EC Glass Driver with Embedded MCU and LIN for High End Mirror |
| MM908E622_08 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Integrated Quad Half-bridge, Triple High Side and EC Glass Driver with Embedded MCU and LIN for High End Mirror |
| MM908E622ACDR2 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Integrated Quad Half-Bridge, Triple High-Side and EC Glass Driver with Embedded MCU and LIN for High End Mirror |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。