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參數(shù)資料
| 型號(hào)： | MM908E621ACDWB/R2 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PDSO54 |
| 封裝： | 17.90 X 7.50 MM, 0.65 MM PITCH, PLASTIC, SOIC-54 |
| 文件頁(yè)數(shù)： | 25/65頁(yè) |
| 文件大?。?/td> | 1221K |
| 代理商： | MM908E621ACDWB/R2 |
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Analog Integrated Circuit Device Data
Freescale Semiconductor
31
908E621
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
Figure 15. Internal Reset Routing
RESET SOURCE
High Temperature Reset
The device is protected against high temperature. When
the chip temperature exceeds a certain temperature, a reset
(HTR) is generated. The reset is flagged by the HTR bit in the
Interrupt Flag Register. A HTR event will reset all registers in
the SPI excluding the RSR.
The HTR can be disabled by bit HTRD in the Interrupt
Mask register.
Note: Disabling the high temperature reset can lead to
destruction of the part in cases of high temperature. This bit
was foreseen for test purposes only!
Watchdog Reset
The watchdog module generates a reset, because of a
watchdog timeout or wrong watchdog timer reset. Reset is
flagged by the WDR bit in the Reset Status Register. A
watchdog reset event will reset all registers in the SPI
excluding the RSR.
Main VREG Low Voltage Reset
The LVR is related to the Main VDD. If the voltage falls
below a certain threshold, it will pull down the RST_A pin.
Reset is flagged by the LVR bit in the Reset Status Register.
An LVR event will reset all register in the SPI excluding the
RSR.
Power On Reset
The POR is related to the internal 5V supply. If the device
detects a power on, the POR bit in the Reset Status Register
(RSR) is set. A power on reset will reset all register in the SPI
including the RSR and set the POR bit.
The Power On Reset circuitry will force the RST_A pin low
for tRST after the VDD has reached its nominal value (above
LVR Threshold). Also see Figure 10, page 20).
Reset Pin / External Reset
An external reset can be applied by pulling down the
RST_A pin. The reset event is flagged by the PINR bit in the
reset status register.
Reset Status Register
This register contains five flags that shows the source of
the last reset. A power-on-reset sets the POR bit and clears
all other bits in the Reset Status Register. All bits can be
cleared by writing a one to the corresponding bit. Uncleared
bits remain set as long as they are not cleared by a power-
on-reset or by software.
In addition, the register includes two flags which will
indicate the source of a wake-up from Sleep mode: Either LIN
bus activity, or an event on the L0 wake-up input pin.
RSR
WDRE
WD Reset Sensor
VDD
RST_A
SPI REGISTERS
Reset SPI Register
(not RSR)
POR internal VREG
LVR Main VREG
HTRD
HTR Reset Sensor
MONO FLOP
Pulse Duration
after reset event is
removed
Clear RSR and set
POR Bit
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