參數(shù)資料
型號： MM908E621ACDWB/R2
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PDSO54
封裝： 17.90 X 7.50 MM, 0.65 MM PITCH, PLASTIC, SOIC-54
文件頁數(shù)： 51/65頁
文件大?。?/td> 1221K
代理商： MM908E621ACDWB/R2
Analog Integrated Circuit Device Data
Freescale Semiconductor
55
908E621
TYPICAL APPLICATIONS
.
Figure 31. Normal Monitor Mode Circuit
Table 20 summarizes the possible configurations and the
necessary setups.
EMC/EMI RECOMMENDATIONS
This paragraph gives some device specific
recommendations to improve EMC/EMI performance.
Further generic design recommendations can be found on
the Freescale web site www.freescale.com.
VSUP Pins (VSUP[1:8])
It is recommended to place a high quality ceramic
decoupling capacitor close to the VSUP pins to improve
EMC/EMI behavior.
MM908E621
RST_A
RST
IRQ_A
IRQ
VSSA/VREFL
VDDA/VREFH
EVDD
VDD
EVSS
VSS
VSUP[1:8]
GND[1:4]
4.7F
100nF
PTC4/OSC1
PTB3/AD3
PTB4/AD4
PTA0/KBD0
PTA1/KBD1
TESTMODE
MAX232
10k
RS232
DB-9
1
3
C1+
C1-
4
5
C2+
C2-
7
8
2
3
5
VCC
GND
16
15
2
V+
V-
6
1F
+
1F
+
1F
+
1F
2
1
3
65
4
74HC125
9.8304MHz CLOCK
VDD
DATA
CLK
VDD
10k
VDD
VTST
VSUP
47F
+
100nF
10
9
T2OUT
R2IN
T2IN
R2OUT
Table 20. Monitor Mode Signal Requirements and Options
Mode
IRQ RST TESTMODE
Reset
Vector
Serial
Communication
Mode
Selection
ICG
COP
Normal
Request
Time-out
Communication Speed
PTA0
PTA1
PTB3
PTB4
External
Clock
Bus
Frequency
Baud
Rate
Normal
Monitor
VTST VDD
1
X
1
0
1
OFF
disabled
9.8304
MHz
2.4576
MHz
9600
Forced
Monitor
VDD
1
$FFFF
(blank)
10
X
OFF
disabled
9.8304
MHz
2.4576
MHz
9600
GND
ON
disabled
—
Nominal
1.6MHz
Nominal
6300
User
VDD
0
not $FFFF
(not blank)
X
ON
enabled
—
Nominal
1.6MHz
Nominal
6300
Notes
33.
PTA0 must have a pullup resistor to VDD in monitor mode
34.
External clock is a 4.9152MHz, 9.8304MHz or 19.6608MHz canned oscillator on OCS1
35.
Communication speed with external clock is depending on external clock value. Baud rate is bus frequency / 256
36.
X = don’t care
37.
VTST is a high voltage VDD +3.5V ≤ VTST ≤ VDD +4.5V
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