參數(shù)資料
型號： ML610Q412P-XXXWA
廠商： LAPIS SEMICONDUCTOR CO LTD
元件分類： 微控制器/微處理器
英文描述： RISC MICROCONTROLLER, UUC95
封裝： 2.83 MM X 2.63 MM, 0.35 MM HEIGHT, 0.80 MM PITCH, DIE-95
文件頁數(shù)： 144/152頁
文件大小： 1641K
代理商： ML610Q412P-XXXWA
ML610Q411/ML610Q412/ML610Q415 User’s Manual
Chapter 6
Clock Generation Circuit
6 – 6
6.3
Description of Operation
6.3.1
Low-Speed Clock
6.3.1.1
Low-Speed Clock Generation Circuit
Figure 6-2 shows the configuration of the low-speed clock generation circuit.
ML610Q411/ML610Q412:
A low-speed clock generation circuit is provided with an external 32.768 kHz crystal. To match the oscillation
frequency by using a trimmer capacitor, connect external capacitors (CGL and CDL) as required.
In STOP mode, VDDX is powered off to stop low-speed oscillation, and the XT0 and XT1 pins become Hiz (Hi
Impedance state). When the ENMLT bit of FCON1 is set to “1”, the 2
× low-speed clock circuit starts to generalte the
LSCLK
×2(64kHz).
ML610Q415:
LSCLK is genrated by the high-speed clock generation circuit and the 1/16 devider. An external crystal oscillator is not
requred. In STOP mode, the high-speed clock oscillation stops. When the ENMLT bit of FCON1 is set to “1”, the 2
×
low-speed clock circuit starts to generate the LSCLK
×2(62.5kHz).
Figure 6-2-1
Circuit Configuration of 32.768 kHz Crystal Oscillation Mode
Figure 6-2-2
Circuit Configuration of 1/16 of 500kHz RC Oscillation Mode
Notes:
Install a crystal as close to the LSI as possible and make sure that signals causing noise and power supply wiring are
not near the crystal and its wiring.
Note that oscillation may stop due to condensation.
STOP mode
Low-speed clock
(LSCLK)
2
× clock
circuit
2
× low-speed clock
(LSCLK~ 2)
ENMLT
High-speed
oscillation circuit
1/16
Devider
XT0
VSS
CDL
CGL
32.768 kHz
crystal
XT1
VDDX
STOP mode
Low-speed clock
(LSCLK)
RF
CD
CG
VSS
VSS
2
× low-speed clock
(LSCLK
×2)
ENMLT
2
× clock
circuit
Control Circuit
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PDF描述
ML610Q411-XXXWA RISC MICROCONTROLLER, UUC95
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