參數資料
型號： ML610Q412P-XXXWA
廠商： LAPIS SEMICONDUCTOR CO LTD
元件分類： 微控制器/微處理器
英文描述： RISC MICROCONTROLLER, UUC95
封裝： 2.83 MM X 2.63 MM, 0.35 MM HEIGHT, 0.80 MM PITCH, DIE-95
文件頁數： 138/152頁
文件大?。?/td> 1641K
代理商： ML610Q412P-XXXWA
ML610Q411/ML610Q412/ML610Q415 User’s Manual
Chapter 6
Clock Generation Circuit
6 – 1
6.
Clock Generation Circuit
6.1
Overview
The clock generation circuit generates and provides a low-speed clock (LSCLK), 2
× low-speed clock (LSCLK2), a
high-speed clock (HSCLK), a system clock (SYSCLK), and a high-speed output clock (OUTCLK).
LSCLK,
LSCLK
×2, and HSCLK are time base clocks for the peripheral circuits, SYSCLK is a basic operation clock of CPU,
and OUTCLK is a clock that is output from a port.
For the OUTCLK output port, see Chapter 19, “Port 2”. Additionally, for the STOP mode described in this chapter, see
Chapter 4, “MCU Control Function”, and for BLD, see Chapter 27, “Battery Level Detection Circuit”.
6.1.1
Features
Low-speed clock: 32.768 kHz crystal oscillation mode
ML610Q411/ML610Q412:
32.768kHz Crystal oscillation mode
Capable of generating LSCLK × 2 (64 kHz) to be used for some peripherals.
ML610Q411/ML610Q412:
1/16 of 500kHz RC oscillation mode (31.25kHz)
Capable of generating LSCLK × 2 (62.5kHz) to be used for some peripherals.
High-speed clock: Software selection
500 kHz RC oscillation mode
External clock input mode (Not available on ML610Q415)
6.1.2
Configuration
Figure 6-1 shows the configuration of the clock generation circuit.
FCON0
: Frequency control register 0
FCON1
: Frequency control register 1
*
1
:Not used on ML610Q415
*
2
:The SYSCLK is fixed to HSCLK on ML610Q415
Figure 6-1
Configuration of Clock Generation Circuit
Note:
This LSI starts operation with a clock generated by dividing the 500 kHz RC oscillation frequency by 8 after power-on
or a system reset.
At initialization by software, set the FCON0 or FCON1 register to switch the clock to a required
one.
Operation of ML610Q411/ ML610Q412 is not guaranteed under a condition where a low-speed clock is not
supplied.
XT0*
1
XT1*
1
High-speed
clock generation
circuit
P10/OSC0
P11/OSC1
Low-speed clock
(LSCLK)
High-speed clock
(HSCLK)
System clock
(SYSCLK)
MPX
FCON0, FCON1
Data bus
Divide ratio
selection
1/1, 1/2, 1/4, 1/8
Divide ratio
selection
1/1, 1/2, 1/4, 1/8
High-speed output clock
(OUTCLK)
OSCLK
Low-speed
clock generation
circuit
2
× low-speed clock
(LSCLK
×2)
*
2
相關PDF資料
PDF描述
ML610Q411-XXXWA RISC MICROCONTROLLER, UUC95
ML610Q422-XXXTBZ03A RISC MICROCONTROLLER, PQFP120
ML610Q422-NNNTBZ03A RISC MICROCONTROLLER, PQFP120
ML610Q421-XXXWA RISC MICROCONTROLLER, UUC116
ML610Q422P-XXXWA RISC MICROCONTROLLER, UUC116
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