參數(shù)資料
型號(hào): ML610Q412P-XXXWA
廠商: LAPIS SEMICONDUCTOR CO LTD
元件分類: 微控制器/微處理器
英文描述: RISC MICROCONTROLLER, UUC95
封裝: 2.83 MM X 2.63 MM, 0.35 MM HEIGHT, 0.80 MM PITCH, DIE-95
文件頁數(shù): 133/152頁
文件大?。?/td> 1641K
代理商: ML610Q412P-XXXWA
ML610Q411/ML610Q412/ML610Q415 User’s Manual
Chapter 5
Interrupts (INTs)
5 – 20
5.3.4
Notes on Interrupt Routine
Notes are different in programming depending on whether a subroutine is called or not by the program in executing an
interrupt routine, whether multiple interrupts are enabled or disabled, and whether such interrupts are maskable or
non-maskable.
State A: Maskable interrupt is being processed
A-1: When a subroutine is not called by the program in executing an interrupt routine
A-1-1: When multiple interrupts are disabled
Processing immediately after the start of interrupt routine execution
No specific notes.
Processing at the end of interrupt routine execution
Specify the RTI instruction to return the contents of the ELR register to the PC and those of the EPSW register
to PSW.
A-1-2: When multiple interrupts are enabled
Processing immediately after the start of interrupt routine execution
Specify “PUSH
ELR, EPSW” to save the interrupt return address and the PSW status in the stack.
Processing at the end of interrupt routine execution
Specify “POP
PC, PSW” instead of the RTI instruction to return the contents of the stack to PC and PSW.
Example of description: State A-1-1
Example of description: State A-1-2
Intrpt_A-1-1:
; A-1-1 state
Intrpt_A-1-2:
; Start
DI
; Disable interrupt
PUSH ELR, EPSW
; Save ELR and EPSW at the
beginning
:
EI
; Enable interrupt
:
RTI
; Return PC from ELR
:
; Return PSW form EPSW
:
; End
:
POP PC, PSW
; Return PC from the stack
; Return PSW from the stack
; End
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