參數(shù)資料
型號(hào)： ML54051
廠商： LAPIS SEMICONDUCTOR CO LTD
元件分類： 存儲(chǔ)控制器/管理單元
英文描述： FLASH MEMORY DRIVE CONTROLLER, PQFP120
封裝： 14 X 14 MM, 0.40 MM PITCH, PLASTIC, TQFP-120
文件頁數(shù)： 36/37頁
文件大小： 304K
代理商： ML54051
Semiconductor
ML54051
4/33
3.2 NAND Flash Memory Interface
Signal Name
maio [7:0]
macle
maale
maren
mawen
marbn
mbio [7:0]
mbcle
mbale
mbren
mbwen
Type
B
O
I
B
O
Pin Count
8
1
8
1
Description
Port A I/O bus
Port A command latch enable signal (signal to control latching of an
operation command into a device)
Port A address latch enable signal (signal to control latching of an address
or input data into a device)
Port A read enable signal
Port A write enable signal (signal to latch data into a device)
Port A ready/busy signal (signal to check internal status of device)
Port B I/O bus
Port B command latch enable signal (signal to control latching of an
operation command into a device)
Port B address latch enable signal (signal to control latching of an address
or input data into a device)
Port B read enable signal
Port B write enable signal (signal to latch data into a device)
mbrbn
I
1
Port B ready/busy signal (signal to check internal status of device)
mctl
I
1
Chip enable signal mode select (mcen[7:0] control)
mcen [7:0]
O
8
Chip enable signals
mct1 = 0 : Chip enable signal
mct1 = 1 : Chip select and chip enable signals
Total 36 pins
mwpn
O
1
Write protect signal (signal to forcibly prohibit write and erase operations)
*
mcen[7:0] performs 2 types of operations depending upon the mctl signal.
If mctl = 0, mcen[7:0] functions as the chip enable signals.
If mctl = 1, mcen[5:1] functions as the chip select signals and mcen[0] functions as the chip
enable signal.
In the latter case, mcen[5:1] and mcen[0] must be connected to an external decoder and
mcen[7:6] are not used.
*
In an external CPU connection mode, mctl and mcen[7:6] function as control signals (xpsen,
xrst, xclk, respectively) for the extended bus.
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