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參數(shù)資料
| 型號(hào)： | ML54051 |
| 廠商： | LAPIS SEMICONDUCTOR CO LTD |
| 元件分類： | 存儲(chǔ)控制器/管理單元 |
| 英文描述： | FLASH MEMORY DRIVE CONTROLLER, PQFP120 |
| 封裝： | 14 X 14 MM, 0.40 MM PITCH, PLASTIC, TQFP-120 |
| 文件頁數(shù)： | 22/37頁 |
| 文件大小： | 304K |
| 代理商： | ML54051 |
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Semiconductor
ML54051
25/33
7.6 Number of Installed Memory Chips and CHS Structure
NAND flash memory is erased in block units. Since block erasing is also performed during a 1-
page (sector) write, efficiency is increased during write operations by serially addressing sectors
within the same block.
The CHS structure and number of installed memory chips when using 64, 128, 256 and 512 Mbit
memory are listed below (where C is the default value). The C value of the CHS address can be
set by the change physical cylinder command (a vendor-unique command).
64 Mbit Memory
Capacity
No. of Chips
CHS
H
LBA Max. (Hex)
CS
8
16
32
48
64
80
96
112
128
144
160
1
2
4
6
8
10
12
14
16
18
20
1000
1
2
3
4
5
6
7
8
9
10
16
32
16000
32000
64000
96000
128000
160000
192000
224000
256000
288000
320000
(3E80)
(7D00)
(FA00)
(17700)
(1F400)
(27100)
(2EE00)
(36B00)
(3E800)
(46500)
(4E200)
128 Mbit Memory
Capacity
No. of Chips
CHS
H
LBA Max. (Hex)
CS
16
32
64
96
128
160
192
224
256
288
320
1
2
4
6
8
10
12
14
16
18
20
1000
1
2
3
4
5
6
7
8
9
10
32
64
32000
64000
128000
192000
256000
320000
384000
448000
512000
576000
640000
(7D00)
(FA00)
(1F400)
(2EE00)
(3E800)
(4E200)
(5DC00)
(6D600)
(7D000)
(8CA00)
(9C400)
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