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參數(shù)資料
| 型號： | MK50H28Q25/XX |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 1 CHANNEL(S), LOCAL AREA NETWORK CONTROLLER, PQCC52 |
| 封裝： | PLASTIC, LCC-52 |
| 文件頁數(shù)： | 44/64頁 |
| 文件大小： | 429K |
| 代理商： | MK50H28Q25/XX |
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4.4.10 Disabling the MK50H28
The following procedure should be followed to disable the MK50H28:
1. Issue the STOP primitive through CSR1. This will disable the MK50H28 from receiving or trans-
mitting. The TD pin will be held high while the MK50H28 is in the Stopped mode. The STOP bit
in CSR0 will be set and interrupts will be disabled. If reception or transmission of a frame is in
progress, then received data may be lost, and the transmitted frame will be aborted.
4.4.11 Re-enabling the MK50H28
The same procedure should be followed for re-enabling the MK50H28 as was used to Initialize upon
power up. If the Initialization Block and the hardware configuration have not changed, then steps 1,2,3,
4 and 5 of the Initialization sequence may be omitted.
4.4.12 MK50H28 Internal Self Test
The MK50H28 contains an easy to use internal self test designed to test, with a high fault coverage, all
of the major blocks of the device except the DMA controller. It is suggested that a loopback test also be
performed to more completely test the DMA controller.
The following procedure should be followed to execute the internal self test:
1. Reset the device using the RESET pin.
2. Set bit 04 of CSR4.
3. Issue a Self Test Request through CSR1.
4. Poll CSR1, waiting for the PAV bit in CSR1 to be set by the MK50H28.
5. After the PAV bit is set, read CSR1. The success or failure of the test is indicated in the PPARM
and PPRIM fields as follows:
PPARM
PPRIM
RESULT
0
Passed self test.
1
Failed the reset test of the self test.
1
2
Failed the self test in the micro controller RAM.
1
3
Failed the self test in the ALU.
1
4
Failed the self test in the timers.
1
5
Failed the self test in the transmitter and/or receiver.
1
6
Failed the self test in the CSR’s and/or bus master.
Otherwise
Failed device.
6. If the PAV bit is not set within 75 msec (SYSCLK = 10MHZ), then the MK50H28 is unable to re-
spond to the Self Test Request and will not complete successfully. If the self test passes, then it
may be immediately re-executed from step 3, otherwise re-execution should proceed from step 1.
MK50H28
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