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參數(shù)資料
| 型號(hào)： | MK50H28Q25/XX |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 1 CHANNEL(S), LOCAL AREA NETWORK CONTROLLER, PQCC52 |
| 封裝： | PLASTIC, LCC-52 |
| 文件頁數(shù)： | 18/64頁 |
| 文件大小： | 429K |
| 代理商： | MK50H28Q25/XX |
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BIT
NAME
DESCRIPTION
05
BSWPC
This bit determines the byte ordering of all ”non-data” DMA transfers. This transfers
refers to any DMA transfers that access memory other than the data buffers themselves.
This includes the Initialization Block, Descriptors, and Status Buffer. It has no effect on
data DMAtransfers. BSWPC allows the MK50H28 to operate with memory organizations
that have bits 07:00 at even addresses and with bits 15:08 at odd addressses or vice
versa. BSWPC is Read/Write and cleared by BUS RESET.
With BSWPC = 0:
Address
With BSWPC = 1:
Address
04:03
BURST
This field determines the maximum number of data transfers performed each time control
of the host bus is obtained. BURST is READ/WRITE and cleared on bus Reset.
*Suggested setting
02
BSWPD
This bit determines the byte ordering of all data DMA transfers. Data transfers are
those to or from a data buffer. BSWPD has no effect on non-data transfers. The effect
of BSWPD on data transfers is the same as that of BSWPC on non-data transfers
(see above). For most applications, including most 68000 based systems, this bit
should be set.
01
ACON
ALE CONTROL defines the assertive state of pin 18 when the MK50H28 is a Bus
Master. ACON is READ/ WRITE and cleared by Bus RESET.
00
BCON
BYTE CONTROL redefines the Byte Mask and Hold I/O pins. BCON is READ/WRITE
and cleared by Bus RESET.
XX0
0
. . .
7
8. . .
15
XX1
8. . .
15
XX0
XX1
0
. . .
7
BURST <1:0>
8 bit mode
16 bit mode
00
2
1
10*
16
8
01
unlimited
ACON
PIN18
NAME
0
ASSERTED HIGH
ALE
1
ASSERTED LOW
AS
BCON
PIN16
PIN15
PIN17
0
BM1
BM0
HOLD
1
BUSAKO
BYTE
BUSRQ
MK50H28
25/64
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