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參數(shù)資料
| 型號： | MK50H28Q25/XX |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 1 CHANNEL(S), LOCAL AREA NETWORK CONTROLLER, PQCC52 |
| 封裝： | PLASTIC, LCC-52 |
| 文件頁數(shù)： | 35/64頁 |
| 文件大?。?/td> | 429K |
| 代理商： | MK50H28Q25/XX |
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4.3.1.2 Receive Message Descriptor 0 (RMD0) For LMI Channel (Contimued)
BIT
NAME
DESCRIPTION
14
EOR
End Of Ring. Setting this bit to 1 indicates that this is the last descriptor in the ring.
13
0
Reserved. Must be written as zero.
12
ELF
End of Long Frame indicates that this is the last buffer used by the MK50H28 for this
frame. ELF=0 indicates that this buffer is one in a chain. ELF=1 indicates the end of the
buffer chain. ELF is set by the MK50H28. When not chaining, ELF will always be one.
11:09
LMI Frame
Type
Received
These bits define the type of frame received, as detailed in the following table:
Bit Encoding (MSB - LSB)
Frame Type
000
SVC Frame or Transparent Mode frame
001
Reserved
010
Full Status Enquiry frame
011
Status Enquiry frame (LIV only)
100
Asynchronous Status Frame
101
Update Status frame
110
Full Status frame
111
Status frame (LIV only)
08
FRER
Frame in Error Bit. This bit is valid only if RBFRS is set in CSR 2. This bit will be set by
the MK50H28 only if an aborted or a bad FCS frame is received.
07:00
RBADR
The High Order 8 address bits of the buffer pointed to by this descriptor. This field is
written by the Host and unchanged by MK50H28.
4.3.1.3 Receive Message Descriptor 1 (RMD1)
1
5
1
4
1
3
0
7
0
8
1
0
1
2
0
1
0
2
0
3
0
4
0
5
0
9
0
6
RBADR<15:00>
0
BIT
NAME
DESCRIPTION
15:01
RBADR
The low order 16 address bits of the receive buffer pointed to by this descriptor.
RBADR is written by the Host CPU and unchanged by MK50H28. The receive buffers
must be word aligned.
MK50H28
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