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參數(shù)資料
| 型號(hào)： | MK2069-04GITR |
| 元件分類(lèi)： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | 160 MHz, OTHER CLOCK GENERATOR, PDSO56 |
| 封裝： | 6.10 MM, 0.50 MM PITCH, TSSOP-56 |
| 文件頁(yè)數(shù)： | 19/19頁(yè) |
| 文件大?。?/td> | 449K |
| 代理商： | MK2069-04GITR |
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VCXO-Based Universal Clock Translator
MDS 2069-04 G
9
Revision 090905
Integr ated Circuit System s l 525 Ra ce Stree t , Sa n Jose, CA 951 26 l te l (4 08) 297 -1 201 l
MK2069-04
Loop Filter Capacitor Type
Loop filters must use specific types of capacitors.
Recommendations for these capacitors can be found at
Input Phase Compensation Circuit
The VCXO PLL includes a special input clock phase
compensation circuit. It is used when changing the
phase of the input clock, which might occur when
selecting a new reference input through the use of an
external clock multiplexer.
The phase compensation circuit allows the VCXO PLL
to quickly lock to the new input clock phase without
producing extra clock cycles or clock wander, assuming
the new clock is at the same frequency.
Input pin CLR controls the phase compensation circuit.
CLR must remain high for normal operation. When
used in conjunction with an external multiplexer (MUX),
CLR should be brought low prior to MUX reselection,
then returned high after MUX reselection. This
prevents the VCXO PLL from attempting to lock to the
new input clock phase associated with the input clock.
When CLR is high, the VCXO PLL operates normally.
When CLR is low, the VCXO PLL charge pump output
is inactivated which means that no charge pump
correction pulses are provided to the loop filter. During
this time, the VCXO frequency is held constant by the
residual charge or voltage on the PLL loop filter,
regardless of the input clock condition. However, the
VCXO frequency will drift over time, eventually to the
minimum pull range of the crystal, due to leak-off of the
loop filter charge. This means that CLR can provide a
holdover function, but only for a very short duration,
typically in milliseconds.
Upon bringing CLR high, the FV Divider is reset and
begins counting upon with the first positive edge of the
new input clock, and the charge pump is re-activated.
By resetting the FV Divider, the memory of the previous
input clock phase is removed from the feedback divider,
eliminating the generation of extra VCLK clock cycles
that would occur if the loop was to re-lock under normal
means. Lock time is also reduced, as is the generation
of clock wander.
By using CLR in this fashion VCLK will align to the input
clock phase with only one or two VCLK cycle slips
resulting. When CLR is not used, the number of VCLK
cycle slips can be as high the FV Divider value.
TCLK is always locked to VCLK regardless of the state
of the CLR input.
Lock Detection
The MK2069-04 includes a lock detection feature that
indicates lock status of VCLK relative to the selected
input reference clock. When phase lock is achieved
(such as following power-up), the LD output goes high.
When phase lock is lost (such as when the input clock
stops, drifts beyond the pullable range of the crystal, or
suddenly shifts in phase), the LD output goes low.
The definition of a “l(fā)ocked” condition is determined by
the user. LD is high when the VCXO PLL phase
detector error is below the user-defined threshold. This
threshold is set by external components RLD and CLD
shown in the Lock Detection Circuit Diagram, below.
To help guard against false lock indications, the LD pin
will go high only when the phase error is below the set
threshold for 8 consecutive phase detector cycles. The
LD pin will go low when the phase error is above the set
threshold for only 1 phase detector cycle.
The lock detector threshold (phase error) is determined
by the following relationship:
(LD Threshold) = 0.6 x R x C
Where:
1 k
< R < 1 M (to avoid excessive noise or
leakage)
C > 50 pF (to avoid excessive error due to stray
capacitance, which can be as much as 10 pF
including Cin of LDC)
Lock Detector Application example:
The desired maximum allowable loop phase error
for a generated 19.44 MHz clock is 100UI which is
5.1
s.
Solution: 5.1
s = (0.001 F) x (8.5 k)
Under ideal conditions, where the VCXO is phase-
locked to a low-jitter reference input, loop phase error is
typically maintained to within a few nanoseconds.
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