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參數(shù)資料
| 型號： | MK2069-04GITR |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | 160 MHz, OTHER CLOCK GENERATOR, PDSO56 |
| 封裝： | 6.10 MM, 0.50 MM PITCH, TSSOP-56 |
| 文件頁數(shù)： | 10/19頁 |
| 文件大?。?/td> | 449K |
| 代理商： | MK2069-04GITR |
VCXO-Based Universal Clock Translator
MDS 2069-04 G
18
Revision 090905
Integr ated Circuit System s l 525 Ra ce Stree t , Sa n Jose, CA 951 26 l te l (4 08) 297 -1 201 l
MK2069-04
Note 1: This is the recommended crystal operating range. A crystal as low as 8 MHz can be used, although
this may result in increased output phase noise.
Note 2: The VCXO crystal will be pulled to its minimum frequency when there is no input clock (CLR = 1)
due to the attempt of the PLL to lock to 0 Hz.
Note 3: The minimum practical phase detector frequency is 1 kHz. Through proper loop filter design lower
input frequencies may be possible. Input frequencies as low as 400 Hz have been tested.
Note 4: A higher input clock frequency can be used when RPV divider = 8.
Note 5: The output of RCLK is a positive pulse with a duration equal to VCLK high time, or half the VCLK
period.
Note 6: Referenced to ICLK, the skews of VCLK, RCLK and TCLK increase together when leakage is
present in the external VCXO PLL loop filter.
Output Rise Time, VCLK and
RCLK
tOR
0.8 to 2.0 V, CL=15 pF
1.5
2
ns
Output Fall Time, VCLK and
RCLK
tOF
2.0 to 0.8 V, CL=15 pF
1.5
2
ns
Output Rise Time, TCLK
tOR
0.8 to 2.0 V, CL=15 pF
0.75
1
ns
Output Fall Time, TCLK
tOF
2.0 to 0.8 V, CL=15 pF
0.75
1
ns
Skew, ICLK to VCLK (Note 6)
tIV
Rising edges, CL=15 pF
-5
2.5
+10
ns
Skew, ICLK to RCLK (Note 6)
tIV
Rising edges, CL=15 pF
+5
10
+20
ns
Skew, ICLK to TCLK (Note 6)
tVT
Rising edges, CL=15 pF
-5
1.5
+10
ns
Nominal Output Impedance
ZOUT
20
Parameter
Symbol
Conditions
Min.
Typ.
Max. Units
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