參數(shù)資料
型號(hào)： MK2069-04GITR
元件分類： 時(shí)鐘產(chǎn)生/分配
英文描述： 160 MHz, OTHER CLOCK GENERATOR, PDSO56
封裝： 6.10 MM, 0.50 MM PITCH, TSSOP-56
文件頁(yè)數(shù)： 16/19頁(yè)
文件大小： 449K
代理商： MK2069-04GITR
VCXO-Based Universal Clock Translator
MDS 2069-04 G
6
Revision 090905
Integr ated Circuit System s l 525 Ra ce Stree t , Sa n Jose, CA 951 26 l te l (4 08) 297 -1 201 l
MK2069-04
Setting the VCXO PLL Loop Response.
The VCXO PLL loop response is determined both by
fixed device characteristics and by variables set by the
user. This includes the values of RS, CS, CP and RSET
as shown in the External VCXO PLL Components
figure on this page.
The VCXO PLL loop bandwidth is approximated by:
Where:
RS = Value of resistor RS in loop filter in Ohms
ICP = Charge pump current in amps
(see table on page 7)
KO = VCXO Gain in Hz/V
(see table on page 8)
SV Divider = 1,2,12 or 16
FV Divider = 1 to 4096
The above equation calculates the “normalized” loop
bandwidth (denoted as “NBW”) which is approximately
equal to the - 3dB bandwidth. NBW does not take into
account the effects of damping factor or the second
pole imposed by CP. It does, however, provide a useful
approximation of filter performance.
To prevent jitter on VCLK due to modulation of the
VCXO PLL by the phase detector frequency, the
following general rule should be observed:
.
The PLL loop damping factor is determined by:
Where:
CS = Value of capacitor CS in loop filter in
Farads
External VCXO PLL Components
In general, the loop damping factor should be 0.7 or
greater to ensure output stability. A higher damping
factor will create less peaking in the passband and will
further assure output stability with the presence of
system and power supply noise. A damping factor of 4
will ensure a passband peak less then 0.2 dB which
may be required for network clock wander transfer
compliance. A higher damping factor may also increase
output clock jitter when there is excess digital noise in
the system application, due to the reduced ability of the
PLL to respond to and therefore compensate for phase
noise ingress.
Notes on setting the value of CP
As another general rule, the following relationship
should be maintained between components CS and CP
in the loop filter:
NBW(VCO PLL)
RS ICP
×
K
O
×
2
π SV Divider
×
FV Divider
×
---------------------------------------------------------------------------
=
NBW(VCO PLL)
f(Phase Detector)
20
---------------------------------------
≤
DF(VCLK)
RS
2
------
I
CP
CS
×
K
O
×
SV Divider
FV Divider
×
--------------------------------------------------------------
×
=
R
SET
C
P
21
22
23
24
1
2
3
4
5
6
7
8
9
10
11
12
13
14
X1
15
16
X2
17
18
LFR
19
LF
20
ISET
25
26
27
28
36
35
34
33
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
32
31
30
29
M
K
2069
XTAL
C
L
C
L
R
S
C
S
Crystal Tuning
Capacitors
Refer to "Crystal Tuning Load
Capacitors" Section
CP
CS
20
------
=
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