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參數(shù)資料
| 型號： | MJE16204 |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | 功率晶體管 |
| 英文描述： | 6 A, 250 V, NPN, Si, POWER TRANSISTOR, TO-220AB |
| 封裝： | CASE 221A-09, 3 PIN |
| 文件頁數(shù)： | 11/12頁 |
| 文件大?。?/td> | 123K |
| 代理商： | MJE16204 |
MJE16204
http://onsemi.com
8
IC, COLLECTOR CURRENT (AMPS)
Figure 10. Typical Collector Current Storage
Time in Deflection Circuit Simulator
t s
,ST
ORAGE
TIME
(ns)
2K
700
200
300
ICI/B1 = 7.5
500
1K
12
7
5
3
10
IC, COLLECTOR CURRENT (AMPS)
Figure 11. Typical Collector Current Fall Time
in Deflection Circuit Simulator
t f,
F
ALL
TIME
(ns)
100
20
50
200
23
5
7
110
30
70
TC = 25°C
ICI/B1 = 7.5
10
TC = 25°C
Figure 12. Deflection Simulator Switching
Waveforms From Circuit in Table 2
IC
0% IB
VCE
tsv
VCE = 20 V
tfi
10% IC(pk)
Figure 13. Definition of Dynamic
Saturation Measurement
TIME (ns)
VCE
DYNAMIC SATURATION TIME
IS MEASURED FROM VCE = 1 V
TO VCE = 5 V
tds
1
4
COLLECT
OR-EMITTER
VOL
TAGE
(VOL
TS)
5
0
3
2
0
90% IC(pk)
DYNAMIC DESATURATIION
The SCANSWITCH series of bipolar power transistors
are specifically designed to meet the unique requirements of
horizontal
deflection
circuits
in
computer
monitor
applications. Historically, deflection transistor design was
focused on minimizing collector current fall time. While fall
time is a valid figure of merit, a more important indicator of
circuit performance as scan rates are increased is a new
characteristic, “dynamic desaturation.” In order to assure a
linear collector current ramp, the output transistor must
remain in hard saturation during storage time and exhibit a
rapid turn–off transition. A sluggish transition results in
serious consequences. As the saturation voltage of the
output transistor increases, the voltage across the yoke
drops. Roll off in the collector current ramp results in
improper beam deflection and distortion of the image at the
right edge of the screen. Design changes have been made in
the structure of the SCANSWITCH series of devices which
minimize the dynamic desaturation interval. Dynamic
desaturation has been defined in terms of the time required
for the VCE to rise from 1.0 to 5.0 volts (Figures 12 and 13)
and typical performance at optimized drive conditions has
been specified. Optimization of device structure results in a
linear collector current ramp, excellent turn–off switching
performance, and significantly lower overall power
dissipation.
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