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參數(shù)資料
| 型號： | MIC502 |
| 廠商： | Micrel Semiconductor,Inc. |
| 元件分類： | FPGA |
| 英文描述： | FPGA - 100000 SYSTEM GATE 2.5 VOLT - NOT RECOMMENDED for NEW DESIGN |
| 中文描述： | 范進(jìn)展信息管理IC |
| 文件頁數(shù)： | 7/11頁 |
| 文件大小： | 130K |
| 代理商： | MIC502 |
May 1999
169
MIC502
MIC502
Functional Description
Oscillator
A capacitor connected to CF determines the frequency of the
internal time base which drives the state-machine logic and
determines the PWM frequency. This operating frequency
will be typically 30Hz to 60Hz. (C
F
= 0.1
μ
F for 30Hz.)
Pulse-Width Modulator
A triangle-wave generator and threshold detector comprise
the internal pulse-width modulator (PWM). The PWM’s out-
put duty-cycle is determined by the higher of V
T1
or V
T2
. A
typical voltage range of 30% to 70% of V
DD
applied to the VT1
and VT2 pins corresponds to 0% to 100% duty-cycle. Since
at least one of the control voltage inputs is generally from a
thermistor-resistor divider connected to V
DD
, the PWM out-
put duty cycle will not be affected by changes in the supply
voltage.
Driver Output
OUT is a complementary push-pull digital output with asym-
metric drive (approximately 10mA source, 1mA sink—see
“Electrical Characteristics”). It is optimized for directly driving
an NPN transistor switch in the fan’s ground-return. See
“Applications Information” for circuit details.
Shutdown/Reset
Internal circuitry automatically performs a reset of the MIC502
when power is applied. The MIC502 may be shut down at any
time by forcing V
T1
below its V
IL
threshold. This is typically
accomplished by connecting the VT1 pin to open-drain or
open-collector logic and results in an immediate and asyn-
chronous shutdown of the MIC502. The OUT and /OTF pins
will float while V
T1
is below V
IL
.
If V
T1
then rises above V
IH
, a device reset occurs. Reset is
equivalent to a power-up condition: the state of /OTF is
cleared, a startup interval is triggered, and normal fan opera-
tion begins.
Startup Interval
Any time the fan is started from the off state (power-on or
coming out of sleep mode or shutdown mode), the PWM
output is automatically forced high for a startup interval of 64
×
t
PWM
. Once the startup interval is complete, PWM operation
will commence and the duty-cycle of the output will be
determined by the higher of V
T1
or V
T2
.
Overtemperature Fault Output
/OTF is an active-low, open-collector logic output. An over-
temperature condition will cause /OTF to be asserted. An
overtemperature condition is determined by V
T1
exceeding
the normal operating range of 30% to 70% of V
DD
by > 7% of
V
DD
. Note that V
OT
is guaranteed by design to always be
higher than V
PWM(max)
.
Sleep Mode
When V
T1
and V
T2
fall below V
SLP
, the system is deemed
capable of operating without fan cooling and the MIC502
enters sleep mode and discontinues fan operation. The
threshold where the MIC502 enters sleep mode is deter-
mined by V
SLP
. Connecting the VSLP pin to ground disables
sleep mode.
Micrel
Once in sleep mode, all device functions cease (/OTF in-
active, PWM output off) unless V
T1
or V
T2
rise above V
WAKE
.
(V
WAKE
= V
SLP
+ V
HYST
.) V
HYST
is a fixed amount of hyster-
esis added to the sleep comparator which prevents erratic
operation around the V
SLP
operating point. The result is
stable and predictable thermostatic action: whenever pos-
sible the fan is shut down to reduce energy consumption and
acoustic noise, but will always be activated if the system
temperature rises.
If the device powers-up or exits its reset state, the fan will not
start unless V
T1
or V
T2
rises above V
WAKE
.
System Operation
Power Up
A complete reset occurs when power is applied.
OUT is off (low) and /OTF is inactive (high/floating).
If V
T1
< V
IL
, the MIC502 remains in shutdown.
The startup interval begins. OUT will be on (high) for 64
clock cycles (64
×
t
PWM
).
Following the startup interval, normal operation begins.
Reset Startup Timer;
Deassert /OTF;
OUT Off (Low).
V
T1
> V
OT
POWER ON
V
T1
< V
IL
NO
NO
OUT Held On (High)
During Startup
Interval.
Startup Interval
Finished
Deassert OUT
(OUT = Low)
YES
NO
Assert /OTF While
V
T1
> V
OT
NORMAL
OPERATION
YES
YES
Figure 3. Power-Up Behavior
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