參數(shù)資料
型號: MIC502
廠商: Micrel Semiconductor,Inc.
元件分類: FPGA
英文描述: FPGA - 100000 SYSTEM GATE 2.5 VOLT - NOT RECOMMENDED for NEW DESIGN
中文描述: 范進(jìn)展信息管理IC
文件頁數(shù): 4/11頁
文件大?。?/td> 130K
代理商: MIC502
MIC502
Micrel
MIC502
166
May 1999
Symbol
Parameter
Condition
Min
Typ
Max
Units
Overtemperature Fault Output
V
OL
I
OH
Active (Low) Output Voltage
I
OL
= 2mA
V
/OTF
= V
DD
0.3
V
Off-State Leakage
1
μ
A
Note 1.
Note 2.
Note 3.
Note 4:
Exceeding the absolute maximum rating may damage the device.
The device is not guaranteed to function outside its operating rating.
Devices are ESD sensitive. Handling precautions recommended.
Part is functional over this V
range; however, it is characterized for operation at 4.5V
V
DD
5.5V and 10.8V
V
DD
13.2V ranges. These
ranges correspond to nominal V
DD
of 5V and 12V, respectively.
Guaranteed by design.
V
OT
is guaranteed by design to always be higher than V
PWM(max)
.
Logic time base and PWM frequency. For other values of C
F
,
f(Hz) = 30Hz0.1 F
Note 5.
Note 6.
Note 7.
C
, where C is in
μ
F.
Timing Diagrams
V
OH
V
OL
0V
50%
80%
40%
0%
100%
40%
70%
t
STARTUP
t
PWM
Output
Duty Cycle
A
B
C
D
E
F
G
0.7V
DD
0.3V
DD
V
T1
V
T2
V
SLP
100%
0%
30%
70%
80%
50%
40%
40%
Input
Signal
Range
V
OT
V
IH
V
IL
0V
V
OH
V
OL
0V
V
OUT
V
OTF
Figure 1. Typical System Behavior
Note A.
Note B.
Note C.
Note D.
Note E.
Note F.
Output duty-cycle is initially determined by V
T1
, as it is greater than V
T2
.
PWM duty-cycle follows V
T1
as it increases.
V
T1
drops below V
T2
. V
T2
now determines the output duty-cycle.
The PWM duty-cycle follows V
T2
as it increases.
Both V
T1
and V
T2
decrease below V
SLP
but above V
IL
. The device enters sleep mode.
The PWM ‘wakes up’ because one of the control inputs (V
in this case) has risen above V
WAKE
. The startup timer is triggered, forcing OUT
high for 64 clock periods. (V
WAKE
= V
SLP
+ V
HYST
. See “Electrical Characteristics.”)
Following the startup interval, the PWM duty-cycle is the higher of V
T1
and V
T2
.
Note G.
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