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| 型號： | MIC502 |
| 廠商： | Micrel Semiconductor,Inc. |
| 元件分類： | FPGA |
| 英文描述： | FPGA - 100000 SYSTEM GATE 2.5 VOLT - NOT RECOMMENDED for NEW DESIGN |
| 中文描述： | 范進展信息管理IC |
| 文件頁數(shù)： | 5/11頁 |
| 文件大?。?/td> | 130K |
| 代理商： | MIC502 |
May 1999
167
MIC502
MIC502
Micrel
V
OH
V
OL
0V
40%
60%
30%
0%
100%
t
STARTUP
t
PWM
Output
Duty Cycle
H
I
J
K
M
N
L
0.7V
DD
0.3V
DD
V
T1
V
T2
V
SLP
100%
0%
20%
60%
40%
30%
PWM
Range
V
OT
V
IH
V
IL
0V
V
OH
V
OL
0V
V
OUT
V
OTF
O
100%
V
DD
0V
V
DD
Figure 2. MIC502 Typical Power-Up System Behavior
Note H.
At power-on, the startup timer forces OUT on for 64 PWM cycles of the internal timebase (t
PWM
). This insures that the fan will start from a
dead stop.
The PWM duty-cycle follows the higher of V
T1
and V
T2,
in the case, V
T1
.
The PWM duty-cycle follows V
T1
as it increases.
PWM duty-cycle is 100% (OUT constantly on) anytime V
T1
> V
PWM(max)
.
/OTF is asserted anytime V
T1
> V
OT
. (The fan continues to run at 100% duty-cycle.)
Note M.
/OTF is deasserted when V
T1
falls below V
OT
; duty-cycle once again follows V
T1
.
Note N.
Duty-cycle follows V
until V
< V
T2
, at which time V
becomes the controlling input signal. Note that V
T1
is below V
SLP
but above V
IH
; so
normal operation continues. (Both V
T1
and V
T2
must be below V
SLP
to active sleep mode.)
Note O.
All functions cease when V
T1
< V
IL
; this occurs regardless of the state of V
T2
.
Note I.
Note J.
Note K.
Note L.
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