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參數(shù)資料
| 型號： | MH28D72KLG-75 |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | 9,663,676,416-BIT (134,217,728-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module |
| 中文描述： | 9663676416位（134217728 - Word的72位），雙數(shù)據(jù)速率同步DRAM模塊 |
| 文件頁數(shù)： | 25/39頁 |
| 文件大?。?/td> | 337K |
| 代理商： | MH28D72KLG-75 |
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MITSUBISHI LSIs
MITSUBISHI ELECTRIC
MH28D72KLG-75,-10
9,663,676,416-BIT (134,217,728-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
MIT-DS-0412-0.1
21.Mar.2001
Preliminary Spec.
Some contents are subject to change without notice.
25
WRITE
After tRCD from the bank activation, a WRITE command can be issued. 1st input data is set from the
WRITE command with data strobe input, following (BL-1) data are written into RAM, when the Burst
Length is BL. The start address is specified by A11,A9-A0, and the address sequence of burst data is
defined by the Burst Type. A WRITE command may be applied to any active bank, so the row precharge
time (tRP) can be hidden behind continuous input data by interleaving the multiple banks. From the last
data to the PRE command, the write recovery time (tWRP) is required. When A10 is high at a WRITE
command, the auto-precharge(WRITEA) is performed. Any command(READ,WRITE,PRE,ACT) to the
same bank is inhibited till the internal precharge is complete. The next ACT command can be issued after
tDAL from the last input data cycle.
WRITE with Auto-Precharge (BL=8)
Command
A0-9,11-12
A10
BA0,1
DQ
ACT
Xa
00
WRITE
1
00
ACT
Xb
00
tRCD
Da0
DQS
/CLK
CLK
Da1
Da2
Da3
Da4
Da5
Da6
Da7
tDAL
Xa
Y
Xb
Multi Bank Interleaving WRITE (BL=8)
Command
A0-9,11-12
A10
BA0,1
DQ
ACT
Xa
00
WRITE
00
WRITE
0
0
10
ACT
Xb
10
0
10
tRCD
tRCD
PRE
0
00
PRE
DQS
/CLK
CLK
Da0
Da1
Da2
Da3
Da4
Da5
Da6
Da7
Db0
Db1
Db2
Db3
Db4
Db5
Db6
Db7
Xa
Ya
Yb
Xb
Module input and output timing.
Module input and output timing.
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