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參數(shù)資料
| 型號(hào)： | MH28D72KLG-75 |
| 廠(chǎng)商： | Mitsubishi Electric Corporation |
| 英文描述： | 9,663,676,416-BIT (134,217,728-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module |
| 中文描述： | 9663676416位（134217728 - Word的72位），雙數(shù)據(jù)速率同步DRAM模塊 |
| 文件頁(yè)數(shù)： | 19/39頁(yè) |
| 文件大小： | 337K |
| 代理商： | MH28D72KLG-75 |
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MITSUBISHI LSIs
MITSUBISHI ELECTRIC
MH28D72KLG-75,-10
9,663,676,416-BIT (134,217,728-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
MIT-DS-0412-0.1
21.Mar.2001
Preliminary Spec.
Some contents are subject to change without notice.
19
18
17
7.8
7.8
1
1
1
1
200
200
80
75
1
1
15
15
15
15
20
20
20
20
80
75
70
65
120,000
50
120,000
45
us
tCK
tCK
tCK
ns
tCK
ns
ns
ns
ns
ns
Average Periodic Refresh interval
tREFI
Exit Power down to -Read command
tXPRD
Exit Power down to command
tXPNR
tXSRD
Exit Self Ref. to -Read command
tXSNR
Exit Self Ref. to non-Read command
tWTR
Internal Write to Read Command Delay
ns
35
35
Auto Precharge write recovery + precharge time
tDAL
-10
-75
AC Characteristics
Max.
Min.
Max.
Min.
Parameter
tWR
Write Recovery time
tRRD
Act to Act Delay time
Row Precharge time
Row to Column Delay
tRP
tRCD
tRFC
Auto Ref. to Active/Auto Ref. command period
ns
Row Cycle time(operation)
tRC
Row Active time
ns
tRAS
Notes
Unit
Symbol
Output Load Condition
(for component measurement)
DQ
Output Timing
Measurement
Reference
Point
V
REF
V
REF
DQS
V
OUT
V
REF
30pF
50ohm
V
TT
=V
REF
Zo=50 ohm
10cm
AC TIMING REQUIREMENTS(Continues)
(Ta=0 ~ 70°C , Vdd = VddQ = 2.5 ± 0.2V, Vss = VssQ = 0V, unless otherwise noted)
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