參數(shù)資料
型號: MD2534-D1G-X-P
廠商: SANDISK CORP
元件分類: 存儲控制器/管理單元
英文描述: FLASH MEMORY DRIVE CONTROLLER, PBGA115
封裝: 12 X 9 MM, 1.20 MM HEIGHT, FBGA-115
文件頁數(shù): 75/87頁
文件大?。?/td> 1675K
代理商: MD2534-D1G-X-P
Rev. 1.2
Product Specifications
mDOC H3 EFD Featuring Embedded TrueFFS Data Sheet
77
92-DS-1205-10
Figure 33: Slave SPI Control Timing
10.3.11
Power Supply Sequence
When operating mDOC H3 with separate power supplies powering the VCCQ, VCC, VCC1 or
VCC2 rails, it is desirable to turn the supplies on and off simultaneously. Providing power to one
supply rail and not the other (either at power-on or power-off) can cause excessive power
dissipation. Damage to the device may result if this condition persists for more than 500 msec.
10.3.12
Power-Up Timing
mDOC H3 is reset by assertion of the RSTIN# input. When this signal is negated, mDOC H3
initiates a download procedure from the flash memory into the internal Programmable Boot
Block. During this procedure, mDOC H3 does not respond to read or write access.
Host systems must therefore observe the requirements described below for initial access to
mDOC H3. Any of the following methods may be employed to guarantee first-access timing
requirements:
Use a software loop to wait at least Tp (BUSY1) before accessing the device after the
reset signal is negated.
Poll the state of the BUSY# output.
Use the BUSY# output to hold the host CPU in wait state before initiating the first access
which will be a RAM read cycle. At least one of the signals CE# and OE# must be kept
negated (high) until BUSY# is negated.
Hosts that use mDOC H3 to boot the system must employ the latter option or use another method
to guarantee the required timing of initial access.
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