參數(shù)資料
型號(hào)： MD2534-D1G-X-P
廠商： SANDISK CORP
元件分類： 存儲(chǔ)控制器/管理單元
英文描述： FLASH MEMORY DRIVE CONTROLLER, PBGA115
封裝： 12 X 9 MM, 1.20 MM HEIGHT, FBGA-115
文件頁(yè)數(shù)： 54/87頁(yè)
文件大小： 1675K
代理商： MD2534-D1G-X-P
Rev. 1.2
Design Considerations
mDOC H3 EFD Featuring Embedded TrueFFS Data Sheet
58
92-DS-1205-10
9.8.2.1
Read Mode
The LATENCY field controls the number of clock cycles between mDOC H3 sampling CE#
being asserted and when the first word of data is available to be latched by the host. This number
of clock cycles is equal to 3 + LATENCY.
WAIT_STATE allows setting the number of CLK after the host has read the last word until the
release of the CE#.
1: One CLK clock before CE# release
2: Two CLK clocks before CE# release
3: Three CLK clocks before CE# release
The HOLD bit in the Burst Mode Control register can be set to hold each data word valid for two
clock cycles rather than one.
Note: If HOLD = 1, then the data is available to be latched on this clock and on the subsequent
clock.
The LENGTH field must be programmed with the length of the burst to be performed (0
corresponds to 4 cycles; 1 to 8 cycles, 2 to 16 and 3 corresponds to 32 cycles). Each burst cycle
must read exactly this number of words.
The CLK input can be toggled continuously or can be halted. When halting the CLK input, the
following guidelines must be observed:
The host must provide a clock signal for the full sequence defined by the LATENCY,
WAIT STATE, HOLD and LENGTH bit fields. The clock can only be stopped after
the release of CE#.
The clock can be halted momentarily during a burst sequence but the host must
provide rising clock edges for the completion of the burst sequence.
Note: For full information regarding the Synchronous Burst Mode see the DOC Driver 1.0 Block
Device (BD) Software Developer Kit (SDK) Developer Guide.
Figure 16: Demux Read Burst Mode
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