參數(shù)資料
型號(hào)： MD2534-D1G-X-P
廠商： SANDISK CORP
元件分類： 存儲(chǔ)控制器/管理單元
英文描述： FLASH MEMORY DRIVE CONTROLLER, PBGA115
封裝： 12 X 9 MM, 1.20 MM HEIGHT, FBGA-115
文件頁(yè)數(shù)： 35/87頁(yè)
文件大小： 1675K
代理商： MD2534-D1G-X-P
Rev. 1.2
mDOC H3 Registers
mDOC H3 EFD Featuring Embedded TrueFFS Data Sheet
40
92-DS-1205-10
7.
M
DOC H3 REGISTERS
This section describes various mDOC H3 registers and their functions.
Table 3: Various mDOC H3 Registers
Address (Hex)
128KB Window
Address (Hex)
8KB Window
Width
(Bits)
Register Name
0030
8
Paged RAM command
0070
8
Paged RAM Select
0080
8
Paged RAM Unique ID Download
9400/9422
1400/1422
16
Chip Identification [0:1]
9402/9424
1402/1424
16
Burst Write/Read Mode Control
9404
1404
16
Burst Write Mode Exit
940C
140C
16
DPD Wakeup Trigger Register
9416
1416
16
DPD Activation Register
940E
140e
16
DMA Control
9418
1418
16
DMA Negation
9410
1410
16
Software Lock
9412
1412
16
Endian Control
7.1
Definition of Terms
The following abbreviations and terms are used within this section:
RFU
Reserved for future use. This bit is undefined during a read cycle and “don’t care”
during a write cycle.
RFU_0
Reserved for future use; when read, this bit always returns the value 0; when
written, software should ensure that this bit is always cleared to 0.
RFU_1
Reserved for future use; when read, this bit always returns the value 1; when
written, software should ensure that this bit is always set to 1.
Reset Value
Refers to the value immediately present after moving from Reset State to one of
the work modes.
7.2
Reset Values
The Reset value written in the register description is the register value after mDOC H3 moves
out from Reset state and enters one of the Work modes. Registers for which a value is not
defined after moving from Reset State to one of the work modes, are marked by an N/A reset
value.
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