參數(shù)資料
型號(hào): MD2534-D1G-X-P
廠商: SANDISK CORP
元件分類(lèi): 存儲(chǔ)控制器/管理單元
英文描述: FLASH MEMORY DRIVE CONTROLLER, PBGA115
封裝: 12 X 9 MM, 1.20 MM HEIGHT, FBGA-115
文件頁(yè)數(shù): 59/87頁(yè)
文件大?。?/td> 1675K
代理商: MD2534-D1G-X-P
Rev. 1.2
Design Considerations
mDOC H3 EFD Featuring Embedded TrueFFS Data Sheet
62
92-DS-1205-10
16-Bit (Word) Data Access Mode
The mDOC H3 is 16 bit wide device. All accesses to and from the device are 16 bit wide.
mDOC H3 address lines should be connected to system host address lines, as depicted in Figure
20. mDOC H3 A0 line should be connected either to system host SA0 address line, or to VSS.
System Host
mDOC H3
SA16
A0
Note:
The prefix “SA” indicates system host address lines
Figure 20: 16-Bit Data Access Mode
32-Bit (Double Word) Data Access Mode
In a 32-bit bus system that cannot execute word-aligned accesses, the system address lines SA0
and SA1 are always 0. Consecutive double words (32-bit words) are differentiated by SA2
toggling. Therefore, in 32-bit systems that support only 32-bit data access cycles, mDOC H3
signal A1 is connected to the first system address bit that toggles; i.e., SA2.
mDOC H3 address lines should be connected to system host address lines, as depicted in Figure
mDOC H3 A0 line should be connected either to system host SA1 address line, or to VSS
System Host
Note:
The prefix “SA” indicates system host address lines
Figure 21: Address Shift Configuration for 32-Bit Data Access Mode
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