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參數(shù)資料
| 型號： | MCZ34701EWR2 |
| 廠商： | 飛思卡爾半導(dǎo)體(中國)有限公司 |
| 英文描述： | 1.5A Switch-Mode Power Supply with Linear Regulator |
| 中文描述： | 1.5A的開關(guān)模式電源，線性穩(wěn)壓器 |
| 文件頁數(shù)： | 26/39頁 |
| 文件大?。?/td> | 528K |
| 代理商： | MCZ34701EWR2 |
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Analog Integrated Circuit Device Data
Freescale Semiconductor
26
34701
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
1.
LDO falls faster than VOUT .
The VOUT uses control
methods (4) and (5) described in the section
Methods
of Control on page 23
.
In the case VIN1 = VIN2, the intrinsic operation turns
on both the buck high side MOSFET and the LDO
external Pass MOSFET, and discharges the VOUT
load capacitor into the VIN supply.
2.
VOUT falls faster than LDO.
The LDO uses control
methods (5) and (6) described in the section
Methods
of Control on page 23
.
Shorted Load
1.
LDO shorted to ground.
The VOUT uses methods (1)
and (2) described in the section
Methods of Control on
page 23
.
2.
VOUT shorted to ground.
The LDO uses control
methods (5) and (6) described in the section
Methods
of Control on page 23
.
3. VIN1 shorted to ground. Device is not working.
4.
VIN2 shorted to ground.
This is equivalent to the
switcher V
OUT
output shorted to ground.
5.
LDO shorted to supply.
No load protection. 34701 is
protected by current limit and thermal shutdown.
6.
VOUT shorted to supply.
No load protection. 34701 is
protected by current limit and thermal shutdown.
LOGIC COMMANDS AND REGISTERS
I
2
C BUS OPERATION
The 34701 device is compatible with the I
2
C interface
standard. SDA and SCL pins are the Serial Data and Serial
Clock pins of the I
2
C bus.
I
2
C COMMAND AND DATA FORMATS
Communication Start
Communication starts with a START condition, followed by
the slave device unique address. The Read/Write (R/W) bit
defines whether the data should be read from or written to the
device (the 34701 operates only as a slave device; therefore,
the R/W bit should always be set to 0). The 34701 responds
by sending the Acknowledge bit (Ack) to the master device.
Figure 20
illustrates the beginning of an I
2
C communication
for a 7-bit slave address.
Figure 20. Communication Start Using 7-Bit Address
Slave Address Definition
34701 has the two least significant address bits (LSB)
defined by the state of the CLKSEL pin (A1) and the ADDR
pin (A0).
Note
The state of the CLKSEL pin also defines the
configuration of the oscillator synchronization CLKSYN pin.
Leaving the CLKSEL pin open or pulling it high defines the
CLKSYN pin as an oscillator output. When the CLKSEL pin
is pulled low, the CLKSYN pin is configured as a
synchronization input for the external clock signal.
This feature allows up to four 34701 ICs to communicate
in the same I
2
C bus, all of them sharing the same high order
address bits. A different combination of the two LSB address
bits A1 and A0 can be assigned to each individual part to
assure its unique address.
Figure 21
illustrates the flexible
addressing feature for a 7-bit address.
Table 6
provides the
definition of the selectable portion of the device address.
When the ADDR pin is used and put to low level, pull the
ADDR pin to ground through a 10k
resistor.
Figure 21. Address Bit Definition for 7-Bit Address
Table 6. Definition of Selectable Portion of Device
Address
Writing Data Into the Slave Device
After the address acknowledgment by the slave, DATA
can be written into the slave registers. The R/W bit must be
set to 0 to allow DATA to be written into the 34702.
Figure 22
shows the data write sequence. Actions performed by the
slave device are grayed.
Figure 22. Data Transfer for Write Operations
S
7-Bit Address
R/W
Ack
CLKSEL Pin
ADDR Pin
A1
A0
Low
Low
0
0
Low
0
1
High (Open)
Low
1
0
High (Open)
High (Open)
1
1
Bits
Fixed Address Selectable
Address
1
0
2
1
A1 A0
3
0
5
1
6
1
1
4
MSB
LSB
S
7-Bit Address
0
Ack
DATA
Ack
(Write)
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