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參數(shù)資料
| 型號： | MCZ34701EWR2 |
| 廠商： | 飛思卡爾半導(dǎo)體(中國)有限公司 |
| 英文描述： | 1.5A Switch-Mode Power Supply with Linear Regulator |
| 中文描述： | 1.5A的開關(guān)模式電源，線性穩(wěn)壓器 |
| 文件頁數(shù)： | 17/39頁 |
| 文件大?。?/td> | 528K |
| 代理商： | MCZ34701EWR2 |
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Analog Integrated Circuit Device Data
Freescale Semiconductor
17
34701
FUNCTIONAL DESCRIPTION
FUNCTIONAL PIN DESCRIPTION
POWER SUPPLY PIN (VDDI)
Internal supply voltage. A ceramic low ESR 1uF 6V X5R or
X7R capacitor is recommended.
ADDRESS PIN (ADDR)
The ADDR pin is used to set the address of the device
when used in an I
2
C communication. This pin can either be
tied to VDDI or grounded through a 10k
resistor. Refer to
I
2
C Bus Operation on page 26
for more information on this
pin.
ENABLE 1 AND 2 PINS (EN1 AND EN2)
These two pins permit positive logic control of the Enable
function and selection of the Power Sequencing mode
concurrently.
Table 5
depicts the EN1 and EN2 function and
Power Sequencing mode selection.
Both EN1 and EN2 pins have internal pull-down resistors
and both can withstand a short circuit to the supply voltage,
6.0V.
RESET TIMER PIN (RT)
The Reset Timer power-up delay (RT) pin is used to set
the delay between the time when the LDO and switcher
outputs are active and stable and the
RST
output is released.
An external resistor and capacitor are used to program the
timer. The power-up delay can be obtained by using the
following formula:
t
D
= 10ms + R
t
C
t
Where R
t
is the Reset Timer programming resistor and C
t
is the Reset Timer programming capacitor, both connected in
parallel from RT to ground.
Note
Observe the maximum C
t
value and expect reduced
accuracy if R
t
is less than 10k
.
RESET OUTPUT PIN (
RST
)
The Reset Control circuit monitors both the switching
regulator and the LDO feedback voltages. It is an open drain
output and has to be pulled up to some supply voltage (e.g.,
the output of the LDO) by an external resistor.
The Reset Control circuit supervises both output
voltages—the linear regulator output V
LDO
and the switching
regulator output V
OUT
. When either of these two regulators
is out of regulation (high or low), the
RST
pin is pulled low.
There is a 20
μ
s delay filter preventing erroneous resets.
During power-up sequencing,
RST
is held low until the Reset
Timer times out.
CLOCK SELECTION PIN (CLKSEL)
This pin sets the CLKSYN pin as either an oscillator output
or a synchronization input pin. The CLKSEL pin is also used
for the I
2
C address selection.
CLOCK SYNCHRONIZATION PIN (CLKSYN)
Oscillator output/synchronization input pin.
Table 5. Operating Mode Selection
EN1
EN2
Operating Mode
0
0
Regulators Disabled
0
1
Standard Power Sequencing
1
0
Inverted Power Sequencing
1
1
No Power Sequencing,
Regulators Enabled
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