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參數(shù)資料
| 型號(hào)： | MCZ33977EG |
| 廠商： | 飛思卡爾半導(dǎo)體(中國)有限公司 |
| 英文描述： | Single Gauge Driver |
| 中文描述： | 單表驅(qū)動(dòng) |
| 文件頁數(shù)： | 20/37頁 |
| 文件大?。?/td> | 402K |
| 代理商： | MCZ33977EG |
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Analog Integrated Circuit Device Data
Freescale Semiconductor
20
33977
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
LOGIC COMMANDS AND REGISTERS
SPI PROTOCOL DESCRIPTION
The SPI interface has a full-duplex, three-wire
synchronous,16-bit serial synchronous interface data
transfer and four I/O lines associated with it: Chip Select
(CS)
,
Serial Clock (SCLK), Serial Input (SI), and Serial Output
(SO). The SI/SO pins of the 33977 follow a first in/first out
(D15/D0) protocol with both input and output words
transferring the most significant bit first. All inputs are
compatible with 5.0 V CMOS logic levels.
CHIP SELECT (CS)
The CS
pin enables communication with the master
device.
When this pin is in a Logic [0] state, the 33977 is capable
of transferring information to, and receiving information from,
the master. The 33977 latches data in from the Input Shift
registers to the addressed registers on the rising edge of CS.
The output driver on the SO pin is enabled when CS
is Logic
[0]. When CS is logic high, signals at the SCLK and SI pins
are ignored and the SO pin is tri-stated (high impedance). CS
will only be transitioned from a Logic [1] state to a Logic [0]
state when SCLK is Logic [0]. CS
has an internal pull-up (I
UP
)
connected to the pin, as specified in the section of the Static
Electrical Characteristics table entitled CONTROL I/O,
[
which is found on page...
deleted for consistent format]
Table 3
. This pin is also used to calibrate the internal clock.
SERIAL CLOCK (SCLK)
SCLK clocks the Internal Shift registers of the 33977
device. The SI pin accepts data into the Input Shift register on
the falling edge of the SCLK signal, while the Serial Output
pin (SO) shifts data information out of the SO line driver on
the rising edge of the SCLK signal. It is important the SCLK
pin be in a Logic [0] state whenever the CS
makes any
transition. SCLK has an internal pull-down (l
DWN
), as
specified in the section
Control I/O
of the Static Electrical
Characteristics, [
which is found on page...
deleted for
consistent format]
Table 3
. When CS
is Logic [1], signals at
the SCLK and SI pins are ignored and SO is tri-stated (high
impedance). Refer to the data transfer timing diagrams in
Figure 11
and
Figure 12.
[figure numbers changed due to
template formatting]
It transitions one time per bit transferred at an operating
frequency, f
SPI
, defined in the SPI Interface Timing section of
the Dynamic Electrical Characteristics
Table 4
. It is idle
between command transfers. The pin is 50 percent duty
cycle, with CMOS logic levels. This signal is used to shift data
to and from the device.
SERIAL OUTPUT (SO)
The SO data pin is a tri-stateable output from the Shift
register. This output will remain tri-stated unless the device is
selected by a low CS signal. The output signal generated will
have CMOS logic levels and the output will transition on the
rising edges of SCLK. The serial output data provides status
feedback and fault information for each output and is returned
MSB first when the device is addressed.
The Status register bits are the first 16 bits shifted out.
Those bits are followed by the message bits clocked in FIFO,
when the device is in a daisy chain connection, or being sent
words [
that are
deleted as PV] multiples of 16 bits. Data is
shifted on the rising edge of the SCLK signal. The SO pin
[
will
deleted as PV] remains in a high impedance state until
the CS
pin is put into a logic low state.
SERIAL INPUT (SI)
The SI pin is the input of the SPI. This input has an internal
active pull-down requiring CMOS logic levels. The serial data
transmitted on this line is a 16-bit control command sent MSB
first, controlling the gauge functions. The master ensures
data is available on the falling edge of SCLK.
Serial input information is read on the falling edge of
SCLK. A 16-bit stream of serial data is required on the SI pin,
beginning with the most significant bit (MSB). Messages [
that
are
deleted as PV] not multiples of 16 bits (e.g., daisy
chained device messages) are ignored. After transmitting a
16-bit word, the CS
pin must be de-asserted (Logic [1]) before
transmitting a new word. SI information is ignored when CS
is in a logic high state.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MCZ33977EG | 制造商:Freescale Semiconductor 功能描述:IC STEPPER MOTOR GAUGE DRIVER SPI |
| MCZ33977EGR2 | 功能描述:馬達(dá)/運(yùn)動(dòng)/點(diǎn)火控制器和驅(qū)動(dòng)器 SINGLE GAUGE DR. LG. PTR RoHS:否 制造商:STMicroelectronics 產(chǎn)品:Stepper Motor Controllers / Drivers 類型:2 Phase Stepper Motor Driver 工作電源電壓:8 V to 45 V 電源電流:0.5 mA 工作溫度:- 25 C to + 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:HTSSOP-28 封裝:Tube |
| MCZ33989EG | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC SBC-HS RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| MCZ33989EG | 制造商:Freescale Semiconductor 功能描述:IC SYSTEM BASIS W/CAN TRANCEIVER |
| MCZ33989EGR2 | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC SBC-HS RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
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