參數(shù)資料
型號(hào): MCZ33970EG
廠商: 飛思卡爾半導(dǎo)體(中國(guó))有限公司
英文描述: Dual Gauge Driver Integrated Circuit with Improved Damping Algorithms
中文描述: 雙計(jì)驅(qū)動(dòng)集成電路與改進(jìn)的阻尼算法
文件頁(yè)數(shù): 7/36頁(yè)
文件大?。?/td> 430K
代理商: MCZ33970EG
Analog Integrated Circuit Device Data
Freescale Semiconductor
7
33970
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics
Characteristics noted under conditions 4.75 V < V
DD
< 5.25 V, -40°C < T
A
< 125°C, GND = 0 V unless otherwise noted. Typical
values noted reflect the approximate parameter means at T
A
= 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
POWER OUTPUT AND CLOCK TIMINGS
SIN, COS Output Turn ON Delay Time (Time from Rising
CS
Enabling
Outputs to Steady State Coil Voltages and Currents)
(14)
t
DLY (ON)
1.0
ms
SIN, COS Output Turn OFF Delay Time (Time from Rising
CS
Disables
Outputs to Steady State Coil Voltages and Currents)
(14)
t
DLY (OFF)
1.0
ms
Uncalibrated Oscillator Cycle Time
t
CLU
t
CLC
0.65
1.0
1.7
μ
s
Calibrated Oscillator Cycle Time
Cal Pulse = 8.0
μ
s, PECCR D4 = Logic [0]
Cal pulse = 8.0
μ
s, PECCR D4 = Logic [1]
1.0
0.9
1.1
1.0
1.2
1.1
μ
s
Maximum Pointer Speed
(15)
V
MAX
400
°/s
Maximum Pointer Acceleration
(15)
A
MAX
4500
°/s
2
SPI INTERFACE TIMING
(16)
Recommended Frequency of SPI Operation
f
SPI
1.0
3.0
MHz
Falling Edge of
CS
to Rising Edge of SCLK (Required Setup Time)
(17)
t
LEAD
50
167
ns
Falling Edge of SCLK to Rising Edge of
CS
(Required Setup Time)
(17)
t
LAG
50
167
ns
SI to Falling Edge of SCLK (Required Setup Time)
(17)
t
S
ISU
25
83
ns
Required High State Duration of SCLK (Required Setup Time)
(17)
t
WSCLKH
167
ns
Required Low State Duration of SCLK (Required Setup Time)
(17)
t
WSCLKL
167
ns
Falling Edge of SCLK to SI (Required Hold Time)
(17)
t
SI
(HOLD)
25
83
ns
SO Rise Time
C
L
= 200 pF
t
R
SO
25
50
ns
SO Fall Time
C
L
= 200 pF
t
F
SO
25
50
ns
SI,
CS
, SCLK, Incoming Signal Rise Time
(18)
t
RSI
50
ns
SI,
CS
, SCLK, Incoming Signal Fall Time
(18)
t
F
SI
50
ns
Falling Edge of
RST
to Rising Edge of
RST
(Required Setup Time)
(17)
t
W
RST
3.0
μ
s
Rising Edge of
CS
to Falling Edge of
CS
(Required Setup Time)
(17)
,
(19)
t
CS
5.0
μ
s
Rising Edge of
RST
to Falling Edge of
CS
(Required Setup Time)
(17)
t
EN
5.0
μ
s
Notes
14.
15.
Maximum specified time for the 33970 is the minimum guaranteed time needed from the microcontroller.
The minimum and maximum value will vary proportionally to the internal clock tolerance. These numbers are based on an ideally
calibrated clock frequency of 1.0 MHz. These are not 100 percent tested.
The device shall meet all SPI interface timing requirements specified in
the SPI Interface Timing section of this table, over the temperature
range specified. Digital interface timing is based on a symmetrical 50 percent duty cycle SCLK Clock Period of 333 ns. The device shall
be fully functional for slower clock speeds. See
Figure 4
and
5
.
The maximum setup time specified for the 33970 is the minimum time needed from the microcontroller to guarantee correct operation.
Rise and Fall time of incoming SI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.
The value is for a 1.0 MHz calibrated internal clock. The value will change proportionally as the internal clock frequency changes
16.
17.
18.
19.
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