- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄359155 > MCZ33889BEG (飛思卡爾半導(dǎo)體(中國)有限公司) System Basis Chip with Low Speed Fault Tolerant CAN Interface PDF資料下載
參數(shù)資料
| 型號(hào)： | MCZ33889BEG |
| 廠商： | 飛思卡爾半導(dǎo)體(中國)有限公司 |
| 英文描述： | System Basis Chip with Low Speed Fault Tolerant CAN Interface |
| 中文描述： | 系統(tǒng)基礎(chǔ)芯片與低速容錯(cuò)CAN接口 |
| 文件頁數(shù)： | 24/60頁 |
| 文件大小： | 705K |
| 代理商： | MCZ33889BEG |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁當(dāng)前第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁
Analog Integrated Circuit Device Data
Freescale Semiconductor
24
33889
FUNCTIONAL DESCRIPTION
INTRODUCTION
FUNCTIONAL DESCRIPTION
INTRODUCTION
The MC33889 is an integrated circuit dedicated to
automotive applications. It includes the following functions:
One full protected voltage regulator with 200 mA total
output current capability.
Driver for external path transistor for V2 regulator function.
Reset, programmable watchdog function
Four operational modes
Wake-up capabilities: Forced wake-up, cyclic sense and
wake-up inputs, CAN and the SPI
Can low speed fault tolerant physical interface.
FUNCTIONAL PIN DESCRIPTION
RECEIVE AND TRANSMIT DATA (RX AND TX)
The RX and TX pins (receive data and transmit data pins,
respectively) are connected to a microcontroller’s CAN
protocol handler. TX is an input and controls the CANH and
CANL line state (dominant when TX is LOW, recessive when
TX is HIGH). RX is an output and reports the bus state (RX
LOW when CAN bus is dominant, HIGH when CAN bus is
recessive).
VOLTAGE REGULATOR ONE (VDD1)
The VDD1 pin is the output pin of the 5.0 V internal
regulator. It can deliver up to 200 mA. This output is protected
against overcurrent and overtemperature. It includes an
overtemperature pre-warning flag, which is set when the
internal regulator temperature exceeds 130°C typical. When
the temperature exceeds the overtemperature shutdown
(170°C typical), the regulator is turned off. VDD1 includes an
undervoltage reset circuitry, which sets the RST pin LOW
when VDD is below the undervoltage reset threshold.
RESET (RST)
The Reset pin RST is an output that is set LOW when the
device is in reset mode. The RST pin is set HIGH when the
device is not in reset mode. RST includes an internal pullup
current source. When RST is LOW, the sink current capability
is limited, allowing RST to be shorted to 5.0 V for software
debug or software download purposes.
INTERRUPT (INT)
The Interrupt pin INT is an output that is set LOW when an
interrupt occurs. INT is enabled using the Interrupt Register
(INTR). When an interrupt occurs, INT stays LOW until the
interrupt source is cleared. INT output also reports a wake-up
event by a 10 sec. typical pulse when the device is in Stop
mode.
GROUND (GND)
This pin is the ground of the integrated circuit.
V2CTRL (V2CTRL)
The V2CTRL pin is the output drive pin for the V2 regulator
connected to the external series pass transistor.
VOLTAGE SUPPLY (VSUP)
The VSUP pin is the battery supply input of the device.
HIGH-SIDE OUTPUT 1 (HS1)
The HS pin is the internal high-side driver output. It is
internally protected against overcurrent and
overtemperature.
LEVEL 0-1 INPUTS (L0: L1)
The L0: L1 pins can be connected to contact switches or
the output of other ICs for external inputs. The input states
can be read by the SPI. These inputs can be used as wake-
up events for the SBC when operating in the Sleep or Stop
mode.
VOLTAGE REGULATOR TWO (V2)
The V2 pin is the input sense for the V2 regulator. It is
connected to the external series pass transistor. V2 is also
the 5.0 V supply of the internal CAN interface. It is possible to
connect V2 to an external 5.0 V regulator or to the VDD
output when no external series pass transistor is used. In this
case, the V2CTRL pin must be left open.
RTH (RTH)
Pin for the connection of the bus termination resistor to
CANH
RTL (RTL)
Pin for the connection of the bus termination resistor to
CANL
CAN HIGH AND CAN LOW OUTPUTS
(CANH AND CANL)
The CAN High and CAN Low pins are the interfaces to the
CAN bus lines. They are controlled by TXD input level, and
the state of CANH and CANL is reported through RXD output.
SYSTEM CLOCK (SCLK)
SCLK is the Serial Data Clock input pin of the serial
peripheral interface.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MCZ33927EK | Transistor; Type: Amplifiers/Bipolar; VCEO (V): -100; Ic (A): -1; Pc (W): 0.9; hFE: 140 to 350; VCE (sat) (V) max: -0.5; Package: TO-92Mod |
| MCZ33970EG | Dual Gauge Driver Integrated Circuit with Improved Damping Algorithms |
| MCZ33976EG | Dual Gauge Driver with Configurable esponse Time |
| MCZ33977EG | Single Gauge Driver |
| MCZ33989EG | System Basis Chip with High-Speed CAN Transceiver |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MCZ33889BEG | 制造商:Freescale Semiconductor 功能描述:IC SYSTEM BASIS W/CAN TRANCEIVER |
| MCZ33889BEG/R2 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:System Basis Chip with Low Speed Fault Tolerant CAN Interface |
| MCZ33889BEGR2 | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC SBC-LITE-LS-CAN RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| MCZ33889DEG | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC SBC-LITE-LS-CAN RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| MCZ33889DEG | 制造商:Freescale Semiconductor 功能描述:IC SYSTEM BASIS W/CAN TRANCEIVER |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。