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| 型號： | MCZ33784EFR2 |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 17/30頁 |
| 文件大小： | 0K |
| 描述： | IC SENSOR DBUS DSI 2.02 16-SOIC |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 類型： | 傳感器接口 |
| 輸入類型： | 模擬 |
| 輸出類型： | 數(shù)字 |
| 接口： | 總線 |
| 電流 - 電源： | 4mA |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-SOIC N |
| 包裝： | 帶卷 (TR) |
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Analog Integrated Circuit Device Data
24
Freescale Semiconductor
33784
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
Figure 17. Format Control Command and Response Format
FORMAT CONTROL REGISTERS
The enhanced DSI Register locations are shown in
Figure 9. The ADDR bits in the Format Control Command
select the Format Control Register to which data is written or
from which data is read. The data is 4 bits.
Table 9. Format Control Registers
CRC POLYNOMIAL
The CRC Taps control the feedback for the CRC
Polynomial. The MSB represents the X3 bit. The LSB
represents X0 or the value 1 if set or 0 if not set. The standard
DSI CRC of X4+1 would be obtained by loading 0001 into the
Format register 0. The X4 pin is always considered on, so
nothing has to be done for it. On a reset or clear, the standard
DSI CRC taps are loaded into these registers.
SEED
The Seed is the starting value loaded into the CRC
checking registers before each transaction starts. The default
DSI seed of 1010 would be selected by loading 1010 into
control register 2. On reset or clear, the standard DSI seed is
loaded into this register.
SHORT-WORD DATA LENGTH
The Short-Word Data Length controls the number of bits of
data in a short word. This can be set to 8 or 10. On a reset or
clear, the value in this register defaults to 8. If a number other
than 8 or 10 is written to the register, it is ignored and the
contents of the register are not changed. The standard DSI
short-word data length would be set by loading 1000 into this
register.
FORMAT SELECTION
The Format selection determines whether the standard
DSI values will be used or the values in the Format register.
The switch to the values in the format registers occurs when
1111 is successfully written to control register 7 in a single
command. If the register is currently cleared, and one of the
data bits is not received as a logic [1], the data in the register
will remain all zeroes and the device will not use the Format
register settings. A switch back to standard DBUS occurs
when a ‘0000’ is successfully written to control register 7. If
the registers bits are all set, and one of the bits is received as
a logic [1], the value of the bits in the register will remain 1111
and the switch back to Standard DSI values will not occur.
This is done to reduce the possibility of switching operation
modes due to a corrupted command. When using the Format
Register settings, any command to change them, other than
this register back to 0000, will be ignored.
Data
Address
Command
Word Type
R/W
ADD
R2
ADD
R1
ADD
R0
Data
3
Data
2
Data
1
Data
0
A3
A2
A1
A0
1010
LW & ELW
Not Valid
SW & ESW (8-bit)
Not Valid
ESW (10-bit)
Response
Word Type
A3
A2
A1
A0
0000
R/W
ADD
R2
ADD
R1
ADD
R0
DAT
A3
DAT
A2
DAT
A1
DAT
A0
LW & ELW
No Response
SW & ESW (8-bit)
No Response
ESW (10-bit)
Legend
A[3:0] = Address bits. The address of the selected device.
R/W = Controls if this is a read or write. Write = 1.
ADDR[2:0] = Pointer to Format control register which is to be accessed.
DATA[3:0] = Data to read from or write to in the pointed to Format
Control Register.
Format Control
Register Address
Description
0
CRC Polynomial
1
Reserved
2
Seed
3
Reserved
4
Reserved
5
Short-Word Data Length
6
Reserved
7
Format Selection
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