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參數(shù)資料
| 型號： | MCZ33780EGR2 |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 27/37頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MASTER DUAL DBUS DIFF 16-SOIC |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 系列： | * |
| 應(yīng)用： | * |
| 接口： | * |
| 電源電壓： | * |
| 封裝/外殼： | 16-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-SOIC W |
| 包裝： | 帶卷 (TR) |
| 安裝類型： | 表面貼裝 |
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Analog Integrated Circuit Device Data
Freescale Semiconductor
33
33780
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
DEV[1:0]–Spread Spectrum Frequency Deviation for
Channel n
These bits control the frequency deviation of the spread
spectrum signalling. DEV [1:0] is recommended to be
programmed to either 10 or 11 whenever the spread
spectrum is enabled. DEV = “00” (the default) and DEV = “01”
(typical 1000 nsec) are optionally available under application
usage.
DEV[1:0] = 10 = Deviation enabled.
DEV[1:0] = 11 = Deviation disabled.
The mode with deviation disabled may be used to achieve
fine control of the bit rate without frequency spreading.
DnOFFSETH and DnOFFSETL REGISTERS
These read/write registers control the spread spectrum
PLL offset value. There are four of these registers, two for
each DBUS channel. The bit assignments are shown in
Figure 34. Dn Spread Spectrum Offset High Register Bit Assignments
Figure 35. Dn Spread Spectrum Offset Low Register Bit Assignments
The OFFSETH[0] and OFFSETL[7:0] register bits control
the updating of the PLL loop center frequency. After reset or
when either of these registers is written to, the spread
spectrum PLL loop goes into fast acquisition mode for 64
cycles. After this, the PLL switches to slow acquisition mode.
The default value of 0 0000 0000 sets the PLL to the
minimum data rate available.
DnSSUD Registers
These read-only registers reflect the spread spectrum PLL
loop 6-bit update count. There are two of these registers, one
for each DBUS channel. The bit assignments are shown in
Figure 36 and Figure 37.
D0SSUD also contains an ID bit in D0SSUD[2] which is
hardwired to logic 1. This bit is a 1 regardless of the state of
the spread-spectrum control bits in DOSSCTRL.
Figure 36. D0 Spread Spectrum Up/Down Register Bit Assignments
Figure 37. Dn Spread Spectrum Up/Down Register Bit Assignments
The SSUD[5:0] value reflects the current state of the PLL
loop up/down counter. This 6-bit value is the control input to
the Center Frequency DAC of Figure 12. This 6-bit value is
normalized to the center frequency of the PLL.A write to the
register will be ignored. The 6-bit SSUD value will be latched
whenever CS transitions low so that the value of SSUD will
not change during an SPI command.
The default value of 10 0000 puts the VCO at the center of
its range to minimize the PLL acquisition time.
SPI Data Bit
Bit 7
6
5
4
3
2
1
0
Read/Write
–
OFFSETH8
Reset
0
SPI Data Bit
Bit 7
6
5
4
3
2
1
0
Read/Write
OFFSETL7 OFFSETL6 OFFSETL5 OFFSETL4 OFFSETL3 OFFSETL2 OFFSETL1 OFFSETL0
Reset
0
SPI Data Bit
Bit 7
6
5
4
3
2
1
0
Read
0
SSUD5
SSUD4
SSUD3
ID
SSUD1
SSUD0
Reset
0
1
0
1
0
SPI Data Bit
Bit 7
6
5
4
3
2
1
0
Read
0
SSUD5
SSUD4
SSUD3
SSUD2
SSUD1
SSUD0
Reset
0
1
0
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| MCZ33781EKR2 | 功能描述:輸入/輸出控制器接口集成電路 DBUS2 MASTER STND RoHS:否 制造商:Silicon Labs 產(chǎn)品: 輸入/輸出端數(shù)量: 工作電源電壓: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-64 封裝:Tray |
| MCZ33784EF | 功能描述:加速計 - 板上安裝 DBUS2 SENSOR INTERFACE RoHS:否 制造商:Murata 傳感軸:Double 加速:12 g 靈敏度: 封裝 / 箱體: 輸出類型:Analog 數(shù)字輸出 - 位數(shù):11 bit 電源電壓-最大:5.25 V 電源電壓-最小:4.75 V 電源電流:4 mA 最大工作溫度:+ 125 C 最小工作溫度:- 40 C |
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