參數(shù)資料
型號(hào)： MCZ33780EGR2
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 17/37頁(yè)
文件大?。?/td> 0K
描述： IC MASTER DUAL DBUS DIFF 16-SOIC
標(biāo)準(zhǔn)包裝： 1,000
系列： *
應(yīng)用： *
接口： *
電源電壓： *
封裝/外殼： 16-SOIC（0.295"，7.50mm 寬）
供應(yīng)商設(shè)備封裝： 16-SOIC W
包裝： 帶卷 (TR)
安裝類型： 表面貼裝
Analog Integrated Circuit Device Data
24
Freescale Semiconductor
33780
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
Figure 19. State Diagram Notation
Figure 20, describes how SPI transfers lead to transmit
FIFO push operations or transfer abort actions. State
transitions in this state machine are synchronous with rising
edges of the SPI clock (SCLK). The initial state, SPI_IDLE, is
entered asynchronously whenever internal reset becomes
active or the SPI chip select (CS) input is de-asserted. Upon
entry to the idle state, the SPI_WRITE signal is deactivated
and the SPI bit counter is set to 7 (it will count down as bits
are received).
When the CS goes low (active), the first SPI transfer will be
a command byte and the first bit indicates a write or read
command. The SPI_WRITE signal takes on the value of this
first bit, and the state machine enters the SPI_CMD_XFER
state, where the remaining bits of the command byte are
received. The last five bits of the command set the initial
value of the register pointer. After the command byte is
complete, the state machine advances to the SPI_BURST
state, which remains active until CS goes high (or the
MC33780 is reset).
In the SPI_BURST state, new SPI characters are read-
from, or written-to-and-read-from, MC33780 registers. If the
control register (or CRC polynomial, CRC seed, CRC length,
or spread spectrum control) is written, an ABORT request is
generated that will immediately stop any DBUS transfer that
was in progress (refer to the DBUS transfer state diagram). If
the DATA register low byte is written, a transmit FIFO push
operation is generated (see transmit FIFO state diagram). If
the DATA register low byte is accessed (read or written) and
there is at least one entry in the receive FIFO, a receive FIFO
pop operation is generated.
When a DBUS transfer results in both an R_FIFO_PUSH
and an X_FIFO_POP, the R_FIFO_PUSH is performed first
to avoid the possibility of the transmit FIFO from getting
ahead of the receive FIFO.
Figure 20. State Diagram of SPI Transfer
Figure 21 describes what happens during DBUS serial
transfers. State transfers in this state machine are
synchronous with positive edges on the scaled DBUS 1/3rd
bit clock and the initial state is WAIT_FRAME_DLY. Initial
entry into this state is caused by a reset, abort, or by enable
becoming inactive. These conditions cause an asynchronous
entry into this state. The exit to the next state,
WAIT_SIG_DLY_0, needs to be synchronous.
SYNCHRONOUS CONDITIONS/
ACTION(S);
IDLE
STATE_1
STATE TRANSITIONS OCCUR
ON POS EDGE OF XXX CLK
ASYNCHRONOUS RESET/
ACTION(S);
SPI_IDLE
SPI_CMD_XFER
SPI_BURST
RSTB ACTIVE or CSB INACTIVE/
SPI_WRITE = 0;
SPI_BIT_PTR = 7;
CSB ACTIVE/
SPI_WRITE= MOSI;
~LAST_SPI_BIT/
SPI_BIT_PTR = SPI_BIT_PTR-1;
~LAST_SPI_BIT/
SPI_BIT_PTR = SPI_BIT_PTR-1;
LAST_SPI_BIT/
SPI_BIT_PTR = 7;
INIT_REG_PTR FROM CMD BITS[4:0]
STATE TRANSITIONS OCCUR
ON POS EDGE OF SCLK
LAST_SPI_BIT/
SPI_BIT_PTR = 7;
REG_PTR = REG_PTR +1 (rolls over to 0 after 21);
if SPI_WRITE & REG_PTR = CTRL or POLY or SEED or LENGTH or SSCTRL then ABORT;
if SPI_WRITE & REG_PTR = DATA_L then X_FIFO_PUSH;
if R_FIFO_NOT_EMPTY & REG_PTR = DATA_L then R_FIFO_POP;
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