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參數(shù)資料
| 型號(hào)： | MCP6S28 |
| 廠商： | Microchip Technology Inc. |
| 元件分類： | FPGA |
| 英文描述： | 400000 SYSTEM GATE 2.5 VOLT FPGA - NOT RECOMMENDED for NEW DESIGN |
| 中文描述： | 單端，軌至軌I / O，低增益美國(guó)PGA |
| 文件頁數(shù)： | 7/43頁 |
| 文件大?。?/td> | 880K |
| 代理商： | MCP6S28 |
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2003 Microchip Technology Inc.
DS21117A-page 7
MCP6S21/2/6/8
1.1
DC Output Voltage Specs / Model
1.1.1
IDEAL MODEL
The ideal PGA output voltage (V
OUT
) is:
EQUATION
(see Figure 1-7). This equation holds when there are
no gain or offset errors and when the V
REF
pin is tied to
a low impedance source (<< 0.1
) at ground potential
(V
SS
= 0V).
1.1.2
LINEAR MODEL
The PGA’s linear region of operation, including offset
and gain errors, is modeled by the line V
O_linear
, shown
in Figure 1-7.
EQUATION
The endpoints of this line are at V
O_ideal
= 0.3V and
V
DD
-0.3V. The gain and offset specifications referred to
in the electrical specifications are related to Figure 1-7,
as follows:
EQUATION
FIGURE 1-7:
the standard condition V
REF
= V
SS
= 0V.
Output Voltage Model with
1.1.3
OUTPUT NON-LINEARITY
Figure 1-8 shows the Integral Non-Linearity (INL) of the
output voltage.
EQUATION
The output non-linearity specification in the electrical
specifications is related to Figure 1-8 by:
EQUATION
FIGURE 1-8:
standard condition V
REF
= V
SS
= 0V.
Output Voltage INL with the
V
O_ideal
GV
IN
=
V
REF
V
SS
0V
=
=
where: G is the nominal gain
V
O_linear
V
REF
G 1
V
SS
g
E
0V
+
=
)
V
IN
0.3V
V
OS
+
–
(
)
0.3V
+
=
=
g
E
100%
V
V
0.6V
–
G V
DD
V
G 1
+
)
----------------–
=
V
OS
g
E
)
------------------------
=
G
T
A
g
E
T
A
---------
=
G
+1
=
0
0
0.3
V
DD
-0.3
V
DD
V
OUT
V
Olnea
V
OUT
(V)
V
IN
(V)
0.3
G
V
DD
- 0.3 V
DD
G
G
V
1
Oidea
V
2
INL
V
OUT
V
O_linear
–
=
V
ONL
max V
V
V
DD
–
}
0.6V
--------------------------------
=
0
V
3
V
4
INL (V)
V
IN
(V)
0.3
G
V
DD
- 0.3 V
DD
G
G
0
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