參數(shù)資料
型號： MCP6S28
廠商： Microchip Technology Inc.
元件分類： FPGA
英文描述： 400000 SYSTEM GATE 2.5 VOLT FPGA - NOT RECOMMENDED for NEW DESIGN
中文描述： 單端，軌至軌I / O，低增益美國PGA
文件頁數(shù)： 4/43頁
文件大小： 880K
代理商： MCP6S28
MCP6S21/2/6/8
DS21117A-page 4
2003 Microchip Technology Inc.
DIGITAL CHARACTERISTICS
Electrical Specifications:
Unless otherwise indicated, T
A
= +25°C, V
DD
= +2.5V to +5.5V, V
SS
= GND, V
REF
= V
SS
, G = +1 V/V,
Input = CH0 = (0.3V)/G, CH1 to CH7 = 0.3V, R
L
= 10 k
to V
DD
/2, C
L
= 60 pF, SI and SCK are tied low, and CS is tied high.
Parameters
Sym
Min
Typ
Max
Units
Conditions
SPI Inputs (CS, SI, SCK)
Logic Threshold, Low
V
IL
I
IL
V
IH
—
0
—
0.3V
DD
+1.0
V
Input Leakage Current
-1.0
—
μA
Logic Threshold, High
0.7V
DD
-1.0
—
V
DD
+1.0
V
Amplifier Output Leakage Current
—
μA
In Shutdown mode
SPI Output (SO, for MCP6S26 and MCP6S28)
Logic Threshold, Low
V
OL
V
OH
V
SS
—
V
SS
+0.4
V
DD
V
I
OL
= 2.1 mA, V
DD
= 5V
I
OH
= -400 μA
Logic Threshold, High
V
DD
-0.5
—
V
SPI Timing
Pin Capacitance
C
PIN
t
RFI
—
10
—
pF
All digital I/O pins
Input Rise/Fall Times (CS, SI, SCK)
—
—
2
μs
Note 1
Output Rise/Fall Times (SO)
t
RFO
t
CSH
—
5
—
ns
MCP6S26 and MCP6S28
CS high time
40
—
—
ns
SCK edge to CS fall setup time
t
CS0
10
—
—
ns
SCK edge when CS is high
CS fall to first SCK edge setup time
t
CSSC
40
—
—
ns
SCK Frequency
f
SCK
t
HI
t
LO
t
SCCS
—
—
10
MHz
V
DD
= 5V
(Note 2)
SCK high time
40
—
—
ns
SCK low time
40
—
—
ns
SCK last edge to CS rise setup time
30
—
—
ns
CS rise to SCK edge setup time
t
CS1
100
—
—
ns
SCK edge when CS is high
SI set-up time
t
SU
t
HD
t
DO
t
SOZ
40
—
—
ns
SI hold time
10
—
—
ns
SCK to SO valid propagation delay
—
—
80
ns
MCP6S26 and MCP6S28
CS rise to SO forced to zero
—
—
80
ns
MCP6S26 and MCP6S28
Channel and Gain Select Timing
Channel Select Time
t
CH
—
1.5
—
μs
CHx = 0.6V, CHy =0.3V, G = 1,
CHx to CHy select
CS
= 0.7V
DD
to
V
OUT
90% point
CHx = 0.3V, G = 5 to G = 1 select,
CS
= 0.7V
DD
to
V
OUT
90% point
Gain Select Time
t
G
—
1
—
μs
Shutdown Mode Timing
Out of Shutdown mode (CS goes
high) to Amplifier Output Turn-on
Time
t
ON
—
3.5
10
μs
CS = 0.7V
DD
to V
OUT
90% point
Into Shutdown mode (CS goes high)
to Amplifier Output High-Z Turn-off
Time
t
OFF
—
1.5
—
μs
CS = 0.7V
DD
to V
OUT
90% point
POR Timing
Power-On Reset power-up time
t
RPU
—
30
—
μs
V
DD
= V
POR
- 0.1V to V
POR
+ 0.1V,
50% V
DD
to 90% V
OUT
point
V
DD
= V
POR
+ 0.1V to V
POR
- 0.1V,
50% V
DD
to 90% V
OUT
point
Power-On Reset power-down time
t
RPD
—
10
—
μs
Note
1:
2:
Not tested in production. Set by design and characterization.
When using the device in the daisy chain configuration, maximum clock frequency is determined by a combination of
propagation delay time (t
DO
≤
80 ns), data input setup time (t
SU
≥
40 ns), SCK high time (t
HI
≥
40 ns), and SCK rise and
fall times of 5 ns. Maximum f
SCK
is, therefore,
≈
5.8 MHz.
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